More 3D Integration Articles

@ The ConFab: Supply chain or supply web for 3D packaging?

Jun 6, 2012 With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session, “Advanced Packaging and Progress in 3D Integration,” focused heavily ...

3D and 2.5D semiconductor packaging technologies @ The ConFab

Jun 6, 2012 As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue “Advanced Packaging and Progress in 3D Integration,” a session focused on the higher I/O density and other performance benefits of adv...

Conference Report: International Interconnect Technology Conference, IITC

Jun 4, 2012

The 15th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.

A virtual IDM concept can unite semiconductor foundries, fabless companies, and packaging houses

Jun 4, 2012

The ConFab 2012, Solid State Technology’s invitation-only meeting of the semiconductor industry, opened today in Las Vegas with a keynote address from John Chen, PhD, VP of technology and foundry operations at Nvidia Corporation.

ECTC: Focus on 3D integration and TSVs

Jun 1, 2012

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).

TSV inspection in 3D advanced packaging applications

Jun 1, 2012

Laser triangulation provides fast, accurate and repeatable 3D measurement of TSV nails and
microbumps. Reza Asgari, Rudolph Technologies, Inc., Flanders, NJ.

Funding the future: Managing the cost of R&D

Jun 1, 2012

One of the big issues now facing the industry is to how best spend limited funding for research and development, when so much needs to be done.

3.5D interposers: PCB replacement?

Jun 1, 2012

At the 15th Symposium on Polymers for Microelectronics (May 8-10 in Wilmington, DE), TSMC and Yole Developpement gave plenary presentations on the use of polymeric materials in wafer-level packaging (WLP) from foundry and overall industry perspectives.

Xilinx relies on stacked silicon interconnect for 28Gbps FPGA

May 31, 2012

Xilinx Inc. (NASDAQ:XLNX) began shipping a 3D heterogeneous all-programmable FPGA, the Virtex-7 H580T FPGA, using its stacked silicon interconnect (SSI) technology to reach up to 16 28Gbps and 72 13.1Gbps transceiver bandwidth.

Ziptronix wafer stacking tech expands to 3D memory devices

May 30, 2012

Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology, which has been proven in image sensor packaging.

IC package revenues outgrow unit shipments through 2016

May 29, 2012

Increased demand for product functionality is driving up IC packaging revenue faster -- a 9.8% compound annual growth rate (CAGR) -- than IC unit growth -- 7.3% CAGR 2010-2016, says New Venture Research (NVR).

MEMS Symposium Report: Chasing 1 Trillion

May 24, 2012

The 10th Annual MEMS Technology Symposium sponsored by MEPTEC (MicroElectronics Packaging and Test Engineering Council) was held May 23 at the San Jose Holiday Inn. This year’s theme was “Sensors: A Foundation for Accelerated MEMS Market Growth to $1 Trillion.”

Invensas debuts high-I/O PoP semiconductor packaging design

May 22, 2012

Invensas Corporation, Tessera subsidiary, debuted bond via array (BVA) technology, an ultra-high-I/O PoP semiconductor packaging alternative to wide-I/O TSV packaging.

Amkor plans semiconductor packaging and test facility in Korea

May 19, 2012

Amkor Technology Inc. (NASDAQ:AMKR) plans to build a state-of-the-art factory and global research and development center in the Incheon Free Economic Zone, which is located in the greater metropolitan area of Seoul, Korea.

"3.5D interposer technology could someday replace PCBs" -- TSMC's Doug Yu

May 15, 2012

TSMC’s Doug Yu challenged the current nomenclature and pronounced that interposer technology should be called “3.5D” instead of 2.5D, since it is and will be capable of much more than the simple 3D packaging stack.

Lithography challenges for leading edge 3D packaging applications

May 7, 2012

The lithography challenges  associated with TSV fabrication for various devices structures are investigated. Warren W. Flack, Manish Ranjan, Gareth Kenyon, Robert Hsieh, Ultratech, Inc., San Jose, CA. John Slabbekoorn, Andy Miller, imec, Leuven, Belgium

David McCann of GLOBALFOUNDRIES to speak at The ConFab 2012

May 3, 2012 Solid State Technology is proud to announce that David McCann will speak at The ConFab 2012. David, the Senior Director for Packaging R&D at GLOBALFOUNDRIES in Malta, New York, will speak on the evolution toward silicon-based interconnect and packaging, which is having profound impact on how ...

What have we done for you lately?

May 1, 2012 This page is usually reserved for a guest editorial by someone in the industry that wants to rant a little bit about the lack of standards in any given area, the need to get young students interested in engineering and the sciences, why fab safety is so important, or answering the call to innovat...

The Micron Memory Cube consortium

May 1, 2012

Micron has joined with Samsung to create the "Hybrid Memory Cube (HMC) Consortium" with fellow founding members Altera, Open Silicon, and Xilinx. IBM will be manufacturing the the logic layer.

Interposer consortium ready to expand at Georgia Tech PRC

Apr 26, 2012

After pioneering low-cost wafer- and panel-based glass and silicon interposers in Phase 1 of its SiGI consortium, Georgia Tech Packaging Research Center is beginning Phase 2 in June.

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