Wide I/O DRAM is pushing thin wafer processing into high-volume manufacturing readiness. Thorsten Matthias, Jürgen Burggraf, Daniel Burgstaller, Markus Wimplinger, and Paul Lindner, EV Group, St. Florian am Inn, Austria.

UltraSource Inc. announced CopperVia, a process that fills vias with pure copper to yield low-cost, high-conductivity, reliable electrical and thermal interconnects in ceramic thin film circuit substrates.

The Full Service Foundry business unit of ams extended its dedicated test solutions for foundry customers, offering known good die (KGD), with customers' complex analog/mixed-signal ICs 100% electrically tested according to their own test specification.

Tohoku University of Sendai, Japan and imec signed a collaboration agreement during the Belgian economic mission to Japan, expanding their R&D into areas such as MRAM and 3D semiconductor packaging.

Advantest is developing a line of fully automated and integrated test and handling solutions for TSV-based 2.5D and 3D packages. The concept model test cell, DIMENSION, integrates a high parallel test cluster along with singulated die and 3D die stack automated handling capabilities.

Singapore’s A*STAR Institute of Microelectronics and semiconductor foundry United Microelectronics Corporation (UMC) will collaborate on through-silicon via (TSV) technology for backside illuminated (BSI) CMOS image sensors (CIS).

Day 3 of the 15th IITC (International Interconnect Technology Conference) opened in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.

Ron Huemoeller of Amkor presented in the Advanced Packaging session of Solid State Technology’s The ConFab. He speaks with editor-in-chief Pete Singer.

The 15^th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.

The ConFab 2012, Solid State Technology’s invitation-only meeting of the semiconductor industry, opened today in Las Vegas with a keynote address from John Chen, PhD, VP of technology and foundry operations at Nvidia Corporation.

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).

At the 15th Symposium on Polymers for Microelectronics (May 8-10 in Wilmington, DE), TSMC and Yole Developpement gave plenary presentations on the use of polymeric materials in wafer-level packaging (WLP) from foundry and overall industry perspectives.

One of the big issues now facing the industry is to how best spend limited funding for research and development, when so much needs to be done.

Laser triangulation provides fast, accurate and repeatable 3D measurement of TSV nails and
microbumps. Reza Asgari, Rudolph Technologies, Inc., Flanders, NJ.

Xilinx Inc. (NASDAQ:XLNX) began shipping a 3D heterogeneous all-programmable FPGA, the Virtex-7 H580T FPGA, using its stacked silicon interconnect (SSI) technology to reach up to 16 28Gbps and 72 13.1Gbps transceiver bandwidth.

Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology, which has been proven in image sensor packaging.