The 15^th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.

The ConFab 2012, Solid State Technology’s invitation-only meeting of the semiconductor industry, opened today in Las Vegas with a keynote address from John Chen, PhD, VP of technology and foundry operations at Nvidia Corporation.

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).

Laser triangulation provides fast, accurate and repeatable 3D measurement of TSV nails and
microbumps. Reza Asgari, Rudolph Technologies, Inc., Flanders, NJ.

One of the big issues now facing the industry is to how best spend limited funding for research and development, when so much needs to be done.

At the 15th Symposium on Polymers for Microelectronics (May 8-10 in Wilmington, DE), TSMC and Yole Developpement gave plenary presentations on the use of polymeric materials in wafer-level packaging (WLP) from foundry and overall industry perspectives.

Xilinx Inc. (NASDAQ:XLNX) began shipping a 3D heterogeneous all-programmable FPGA, the Virtex-7 H580T FPGA, using its stacked silicon interconnect (SSI) technology to reach up to 16 28Gbps and 72 13.1Gbps transceiver bandwidth.

Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology, which has been proven in image sensor packaging.

Increased demand for product functionality is driving up IC packaging revenue faster -- a 9.8% compound annual growth rate (CAGR) -- than IC unit growth -- 7.3% CAGR 2010-2016, says New Venture Research (NVR).

The 10^th Annual MEMS Technology Symposium sponsored by MEPTEC (MicroElectronics Packaging and Test Engineering Council) was held May 23 at the San Jose Holiday Inn. This year’s theme was “Sensors: A Foundation for Accelerated MEMS Market Growth to $1 Trillion.”

Invensas Corporation, Tessera subsidiary, debuted bond via array (BVA) technology, an ultra-high-I/O PoP semiconductor packaging alternative to wide-I/O TSV packaging.

Amkor Technology Inc. (NASDAQ:AMKR) plans to build a state-of-the-art factory and global research and development center in the Incheon Free Economic Zone, which is located in the greater metropolitan area of Seoul, Korea.

TSMC’s Doug Yu challenged the current nomenclature and pronounced that interposer technology should be called “3.5D” instead of 2.5D, since it is and will be capable of much more than the simple 3D packaging stack.

The lithography challenges  associated with TSV fabrication for various devices structures are investigated. Warren W. Flack, Manish Ranjan, Gareth Kenyon, Robert Hsieh, Ultratech, Inc., San Jose, CA. John Slabbekoorn, Andy Miller, imec, Leuven, Belgium

Micron has joined with Samsung to create the "Hybrid Memory Cube (HMC) Consortium" with fellow founding members Altera, Open Silicon, and Xilinx. IBM will be manufacturing the the logic layer.

After pioneering low-cost wafer- and panel-based glass and silicon interposers in Phase 1 of its SiGI consortium, Georgia Tech Packaging Research Center is beginning Phase 2 in June.