As packaging has played a larger and larger role in chip performance, form factor, and capabilities, Solid State Technology's The ConFab has increased its focus on back-end processes.

SEMICON West is taking place July 10-12 at the Moscone Center in San Francisco, CA.

UNISEM relaunched its business model with the name “Unisem 2.0.” The company’s aims include lean manufacturing, a focus on the “right” Tier-1 customers, product and technology development in pursuit of high growth rates and margins, and more.

Ultratech acquired IBM patents on semiconductor packaging technologies, including C4 bumping, ball grid array (BGA) methods, lead-free solders, and 3D packaging.

Solid State Technology is hosting 3D and 2.5D Integration: A Status Report, sponsored by EVG and ALLVIA, and is free for all attendees. This preview shares a sneak peek at “Markets for 2.5D and 3D TSV,” presented by E. Jan Vardaman, TechSearch International.

Solid State Technology is hosting a free webcast, 3D and 2.5D Integration: A Status Report. A fourth presenter has just been announced, Brent Przybus, Senior Director, Product Line Marketing, Xilinx Inc.

Dow Corning will collaborate with SUSS MicroTec on a temporary bonding process (materials and equipment) for through-silicon vias (TSV) in high-volume advanced semiconductor packaging.

Solid State Technology will present 3D and 2.5D Integration: A Status Report on June 27, free for all attendees. William Chen, ASE, will join speakers David McCann, GLOBALFOUNDRIES and E. Jan Vardaman, TechSearch International.

In a webcast scheduled for June 27^th at 1:00 Eastern, 11:00 Pacific, David McCann of GLOBALFOUNDRIES will provide a status report on advanced packaging and 3D integration. McCann is responsible for Packaging R&D and back-end strategy and implementation at GLOBALFOUNDRIES.

DARPA’s Intrachip/Interchip Enhanced Cooling (ICECool) program is tasked with bringing “embedded” thermal management to advanced and high-power packages, reducing the size and weight of military electronics systems.

Attendance was high at this year's Electronic Component Technology Conference (ECTC) in San Diego. Sandra Winkler is senior industry analyst at New Venture Research and IEEE/CPMT Luncheon Program Chair, shares the key trends in ECTC's sessions, like WLP, 2.5D, LED packaging, and more.

Wide I/O DRAM is pushing thin wafer processing into high-volume manufacturing readiness. Thorsten Matthias, Jürgen Burggraf, Daniel Burgstaller, Markus Wimplinger, and Paul Lindner, EV Group, St. Florian am Inn, Austria.

UltraSource Inc. announced CopperVia, a process that fills vias with pure copper to yield low-cost, high-conductivity, reliable electrical and thermal interconnects in ceramic thin film circuit substrates.

The Full Service Foundry business unit of ams extended its dedicated test solutions for foundry customers, offering known good die (KGD), with customers' complex analog/mixed-signal ICs 100% electrically tested according to their own test specification.

Tohoku University of Sendai, Japan and imec signed a collaboration agreement during the Belgian economic mission to Japan, expanding their R&D into areas such as MRAM and 3D semiconductor packaging.

Advantest is developing a line of fully automated and integrated test and handling solutions for TSV-based 2.5D and 3D packages. The concept model test cell, DIMENSION, integrates a high parallel test cluster along with singulated die and 3D die stack automated handling capabilities.

Singapore’s A*STAR Institute of Microelectronics and semiconductor foundry United Microelectronics Corporation (UMC) will collaborate on through-silicon via (TSV) technology for backside illuminated (BSI) CMOS image sensors (CIS).

Day 3 of the 15th IITC (International Interconnect Technology Conference) opened in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.