The structure of the industry is rapidly changing — and how it will respond to the simultaneous challenges of Moore's Law scaling, 450mm wafer production, 3D-ICs, and industry consolidation is very much unknown.

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM).

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP, a brain-like function.

At the upcoming International Electron Device Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed.

SPTS' Delta fxP cluster system achieves low-temperature deposition of TEOS oxides and nitrides for via-reveal passivation in 3D IC packaging, solving two key problems of low temperatures and bonding adhesive outgassing.

The 58th annual IEDM will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.

Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.

The National Institute of Standards and Technology (NIST) says it's combined scanning techniques and statistical data to both more precisely and less expensively measure features on a chip -- and two big chip firms are already on board.

EV Group's updated modular EVG150 high-volume coater/developer adds new modules for conformal coating of high topography surfaces, and coating surfaces with vertical sidewall angles, such as through-silicon vias (TSV).

Singapore's Institute of Microelectronics (IME) and MOSIS have signed a memorandum of understanding (MOU) to offer a multiple-project wafer service targeting silicon integrated photonics.

At ECTC 2012, Toray presented results of their study on suppressing wafer level underfill (WUF) material entrapment at copper pillar/pad joints.

Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology and IP reports on recent progress on low temperature (less than 400°C) bonding and cleaving processes.

Rambus Inc. (NASDAQ:RMBS), a technology licensing company, will undergo a restructuring and related cost saving measures to cut its expenses by$30-35 million annually.

ASMC 2013, the leading international technical conference for exploring solutions to improve collective microelectronics manufacturing expertise, has issued a call for papers.

Tessera received an initial payment of approximately $20 million from semiconductor packaging company Amkor, related to the interim award issued by the International Court of Arbitration of the International Chamber of Commerce (ICC).

The Hybrid Memory Cube Consortium released the initial draft of the Hybrid Memory Cube (HMC) interface specification, with the final version planned for end of 2012.

In this SEMI News and Views blog, Karen Savala covers EUV lithography, 450mm wafers, and 3D IC developments, based on her recent presentation at SEMICON West, “Supply Chain Readiness in an Era of Accelerated Change.”