With the approach of full commercial production of 3DIC products, Dr. Phil Garrou shifts his attention to thermal performance questions and proposed thermal solutions for the future.

Fraunhofer IZM's All Silicon System Integration Dresden (ASSID) center will add SPTS' etch and PECVD process capabilities to investigate low-temperature dielectric films for through-silicon vias (TSV) in 3D IC packaging.

SEMI has extended the deadline to submit proposed papers to next spring's China Semiconductor Technology International Conference 2013, and added a new symposium on circuit design, system integration, and application.

The Global Semiconductor Alliance (GSA) says it has formed a Technology Steering Committee to help address key business and technology areas of interest to its members, and "encourage the advancement and adoption of leading technology and practices."

The advent of leading-edge semiconductor packaging technologies dictates efficient use of capital, and only the top-tier semiconductor assembly and test services (SATS) companies will have the financial wherewithal to develop required expertise and capacity, says one analyst.

Nanium says it has shipped its 200 millionth embedded wafer-level ball grid array technology (eWLB) component, a 10% year-over-year productivity increase that reflects full conversion to the company's eWLB overmold technology that allows thinner and more robust packages.

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.”

Sand 9 is partnering with GlobalFoundries for high-volume manufacturing of its microelectromechanical systems (MEMS) timing technology, which incorporates silicon-on-insulator (SOI) and through-silicon vias (TSV).

Tezzaron Semiconductor is taking over SVTC Technologies' wafer fab in Austin, TX, amid reports that the semiconductor/MEMS development organization is cutting back activities in Austin and in California.

The structure of the industry is rapidly changing — and how it will respond to the simultaneous challenges of Moore's Law scaling, 450mm wafer production, 3D-ICs, and industry consolidation is very much unknown.

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM).

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP, a brain-like function.

At the upcoming International Electron Device Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed.

SPTS' Delta fxP cluster system achieves low-temperature deposition of TEOS oxides and nitrides for via-reveal passivation in 3D IC packaging, solving two key problems of low temperatures and bonding adhesive outgassing.

The 58th annual IEDM will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.

Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.

The National Institute of Standards and Technology (NIST) says it's combined scanning techniques and statistical data to both more precisely and less expensively measure features on a chip -- and two big chip firms are already on board.

EV Group's updated modular EVG150 high-volume coater/developer adds new modules for conformal coating of high topography surfaces, and coating surfaces with vertical sidewall angles, such as through-silicon vias (TSV).