More 3D Integration Articles
3D integration: Bringing it home with supply-chain buy-in
May 19, 2011
A recurring theme at this year's Confab is that 3D integration shows tremendous promise, particularly with many fabless companies, yet many barriers remain -- and the first and biggest is preparing the supply chain. |
Non-planar device scaling: SEMATECH talks TSV, SoC, SiP
May 18, 2011
The semiconductor industry is moving to 3D device structures, says Raj Jammy, SEMATECH, at The ConFab 2011, discussing TSV and system-in-package (SiP) opportunities and challenges. He also summarizes logic and memory roadmaps. |
ASMC 2011: Approaching device scaling, manufacturing challenges with partnerships
May 18, 2011
Another eventful (but still rainy) day at this week's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (May 16-18) offered two highlights sharing a theme: how partnerships can address challenges in device scaling and manufacturing. |
Alchimer wet deposition debut targets RDL, other 3D IC processes
May 18, 2011
Alchimer's wet-deposition process, AquiVantage, grows interconnect layers for interposer redistribution layers (RDLs) and significantly enhances via-last backside wafer interconnects. The process eliminates 2 costly photolithography steps. |
Trade-offs and infrastructure are keys to device scaling
May 18, 2011
Raj Jammy, VP of materials and emerging technologies at SEMATECH, covered a broad swath of CMOS scaling drivers, system and device trends, and infrastructure requirements. |
ASMC 2011: Rain doesn't damper the spirit
May 17, 2011
Intermolecular's John Behnke offers his impressions from Day 1 of this year's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) in New York. Highlights: a keynote from a suddenly famous GlobalFoundries exec, on-the-fly edge inspection, equipment health monitoring, and a TSV overview.
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Customers, logic reshaping supplier collaboration landscape
May 17, 2011
Harvey Frye, vice-chairman of TEL America, summarized the new supplier landscape in his Confab talk, taking both a macro point of view of trends, and how his company as a top supplier is addressing them: collaboration among suppliers, and an increasing focus on consumer needs. |
More Moore & More than Moore require fabless, foundry, and packaging houses on board
May 16, 2011
Today at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."
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3D packaging disrupts the IC supply chain -- ConFab session dedicated to the OSAT/foundry/fabless relationship
May 13, 2011
The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from A...
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Day 2, 3 talks on process integration, reliability, 3Di
May 11, 2011
John Iacoponi, IITC 2011 co-chair, reviews Day 2-3 discussions at IITC/MAM, including interconnect reliability, BEOL memory, 3D integration, process integration, ultralow-k, and future-looking talks on graphene and carbon nanotubes. |
SRC attacks 3DIC reliability, design tools with new effort
May 5, 2011
Semiconductor Research Corporation is leading an effort to address key roadblocks for wide-scale adoption of the emerging 3D ICs and systems. These new initiatives will address critical reliability and design tool issues and leverage partnership between researchers from universities and the semic...
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CdTe lab-to-fab: Interviews with NIST, GE at MRS Spring
May 3, 2011
Dr. Fred Seymour, PrimeStar Solar, a wholly owned subsidiary of GE, describes how the company is defining its factory design optimization parameters as it ramps CdTe manufacturing. Dr. Daniel Josell, NIST, discusses how 3D architecture is used to achieve lateral carrier separation, and back-...
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3D IC toolset readiness, Cu bonding, interposer failings
May 1, 2011
The recent IMAPS Global Business Council Meeting and Device Packaging Conference (mid-March in Ft. McDowell, AZ) was the source of some significant new developments in the areas of 3D IC and fan-out wafer-level packaging.
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Pioneering new devices and materials for future ICs
May 1, 2011
It is expected that from the 15nm node on, the industry will need to adopt new transister architectures; among the contenders: FinFETs and TunnelFETs. Thomas Hoffmann, imec, Leuven, Belguim
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IBM to use water cooling for future 3D IC processors
May 1, 2011
At the recent CeBIT Fair in Hanover, Germany, IBM CEO Sam Palmisano announced that IBM's 3D technology will likely appear in its Power8 processor, planned for 2013, using 28nm or 22nm process technology.
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3D CT X-ray imaging fills inspection gaps, says Xradia
May 1, 2011
Xradia has unveiled its latest micro computed tomography (CT) 3D X-ray imaging system, the VersaXRM, targeting gaps in the semiconductor, materials science, geomaterials, and life sciences market segments.
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Electronics packaging leaders gathered under cherry blossoms at ICEP
Apr 21, 2011
T.Onishi, Grand Joint Tech and E.J. Vardaman, TechSearch International share the highlights on low-k dielectrics, 3D packaging, copper pillar, and other exciting work presented at the International Conference on Electronics Packaging (ICEP) in Japan.
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Silicon interposer cost redux goal of GA Tech consortium
Apr 20, 2011
Georgia Tech PRC believes current silicon interposers are limited in performance by high electrical loss of silicon and high cost of wafer-based interposers. Georgia Tech PRC has undertaken silicon R&D with the potential to reduce the cost by 5-10x, in the Silicon and Glass Interposer Industr...
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CEA Leti deploys EVG's litho, packaging tools for 300mm line
Apr 19, 2011
CEA-Leti has installed multiple EVG tools in its 300-mm cleanroom dedicated to R&D and prototyping for 3D integration applications. EVG's equipment will be used in 3D technology demonstrations for Leti's global customer base, as well as low-volume pilot production on 300mm wafers. |
STATS ChipPAC expands TSV service with mid end flow
Apr 19, 2011
STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities. |