2.5D, 3D and Beyond - Bringing 3D Integration to the Packaging Mainstream will take place November 9 in Santa Clara, CA. The MEPTEC conference follows the trend of 3D and 2.5D packaging moving from roadmap to factory production.

The 2012 Symposia on VLSI Technology & Circuits, to be held in Hawaii, June 12-14 (Technology) and 13-15 (Circuits), will accept innovative, original work on microelectronics, ranging from gate stacks and advanced lithography to 3D packaging.

Nanotech accelerator SVTC Technologies, wet chem equipment maker Amerimade Technology, and chemicals company Shanghai Sinyang Semiconductor Materials will collaborate on electroplating processes for TSV that are production-ready for advanced packages and MEMS.

SUSS MicroTec, in partnership with temporary bonding adhesive maker TMAT, will deliver SUSS MicroTec's new-generation high-volume temporary wafer bond tool clusters to a leading IDM.

EV Group (EVG) will work with Fraunhofer IZM's ASSID research center to develop temporary bonding/debonding technologies for thicker die structures, some as large as 600µm thick.

STMicroelectronics (NYSE:STM) has implemented through-silicon vias (TSV) in high-volume micro electro mechanical system (MEMS) devices. ST is using TSV in its smart sensors and multi-axis inertial modules.

All Silicon System Integration Dresden (ASSID) installed an Altatech 300mm CVD tool for dielectric film deposition on advanced through silicon vias (TSV), with diameters as small as 10µm and aspect ratios of 10:1.

Thanks to MEMS, 3D packaging, LEDs, power devices, and other applications, thinned wafers will be the majority of wafers in the market by 2016, according to Yole Développement's new report Thin Wafer Market & Applications. Today, 27% of all processed semiconductors are thinned.

Rudolph Technologies Inc. (NASDAQ:RTEC) shipped its Wafer Scanner 3880 3D Inspection System, multiple NSX Macro Defect Inspection Systems and its Discover Yield Management Software Suite to a leading semiconductor manufacturer for use in developing through silicon via (TSV) structures.

Samsung Electronics Co. Ltd. developed a high-performance 64GB embedded memory with 64Gb NAND. The package contains an 8 die stack in a low profile for smartphones, tablets and other mobile devices.

The first annual Global Interposer Technology Workshop at Georgia Tech will convene students, academics, researchers, and industry to share information on silicon and glass interposers for semiconductor packaging.

Dr. Phil Garrou takes a closer look at highlights from a SiP summit at the recent SEMICON Taiwan: Xilinx FPGAs and Elpida's low-power DDR3 memory.

The Burn-in & Test Socket Workshop (BiTS Workshop) is changing its name to The Burn-in & Test Strategies Workshop to reflect the "evolution of packaged ICs."

Invensas Corporation, a Tessera subsidiary, will demonstrate dual-face down implementation of its new multi-die face-down packaging technology at the Intel Developer's Forum. The multi-die package is wire bonded, mounting ICs upside down and staggering them in a shingle-like configuration.

Forget "3D stacking" -- the two companies say a special electronic "glue" applied to the wafer will help stack dozens of chips into a "silicon skyscraper" that will be much faster and more efficient than current chip technology.

Alchimer's AquiVia film-deposition technology promises to cut fill deposition times and cost even with complex through-silicon via (TSV) 3D packaging structures. The product targets TSV ramp-up at production levels, according to the company.

More than a hundred attendees gathered at a Suss MicroTec workshop at this year's SEMICON West ("3D Integration: Are we there yet?") to hear technical experts from around the globe to present updates on the status of 3D IC packaging.