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Achieving Thermal Control for Power Devices: Die Attach Solder Pastes for Varying Requirements
Not only are today’s package designers and assemblers faced with the inherent design and functionality challenges associated with smaller device footprints and higher I/O counts, but they must also ensure that proper thermal control is built into advanced electronics packages. In fact, heat management for modern power semiconductor devices such as rectifiers, power transistors, amplifiers and countless other consumer and automotive applications is one of the most pressing issues facing the packaging industry. As these packages marry smaller outlines with higher functions, ensuring efficient thermal management will be key to long-term reliability and performance. (Mar 3, 2010, Henkel Corporation) |
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Photovoltaic Modules get a Charge from New Electrically Conductive Adhesives
For high reliability applications such as satellite, automotive, medical and telecom products, electrically conductive adhesives are often used as an alternative to traditional solders. Their benefits are many but, for these applications, conductive adhesives deliver low temperature processing, fine-pitch capability and improved thermal cycling resistance. These advantages are arguably compelling, but electrically conductive adhesives have had limited success on common electronic metals such as copper and Sn and, therefore, have been used most often on noble metallizations like gold and silver palladium on ceramic substrates. While conductive adhesives may also provide benefits to the thin film solar cell market and the silicon solar cell segment, their limitations on copper and Sn have slowed their adoption. (Jan 29, 2010, Henkel Corporation) |
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New Lead-Free Alloy that Takes Under-the-Hood Heat in Stride-Innovative Formulation Provides High Reliability for High-Temp Applications
While lead-free processes now seem like yesterday’s news and the electronics industry |
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How "Free" is Your Halogen-Free Solder Paste?
With all the talk of halogen-free in the electronics industry these days, it’s hard to believe |
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Using Hansen Space to Optimize Solvent Based Cleaning Processes
What is an optimized cleaning process? Is it based solely upon removing the residue, or is it more? Of course it is more. We do not want to remove the labels or other parts markings, or degrade or damage the substrate of individual components. It is not desirable to swell elastomers or create new residues or otherwise affect the product being built. Dissolving manufacturing residues, without affecting the materials of construction, is difficult when working with organic solvents and solvent blends. Water being the great solvent that it is, is all around us. We generally design our widgets to be compatible with water. On the other hand, solvents and solvent blends are not routinely found in the environment in which our widgets are used. Why would a designer design a widget to be tolerant of organic solvents? (Jun 15, 2009, Austin American Technology Corp.) |
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Using Hansen Space to Optimize Solvent Based Cleaning Processes
What is an optimized cleaning process? Is it based solely upon removing the residue, or is it more? Of course it is more. We do not want to remove the labels or other parts markings, or degrade or damage the substrate of individual components. It is not desirable to swell elastomers or create new residues or otherwise affect the product being built. Dissolving manufacturing residues, without affecting the materials of construction, is difficult when working with organic solvents and solvent blends. Water being the great solvent that it is, is all around us. We generally design our widgets to be compatible with water. On the other hand, solvents and solvent blends are not routinely found in the environment in which our widgets are used. Why would a designer design a widget to be tolerant of organic solvents? (Jun 15, 2009, Austin American Technology Corp.) |
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Breakthrough Package-Level Lead-Free Alloy Addresses Board-Level Alloy Challenges Not all SAC alloys are created equal: Especially when attempting to use board-level recommended SAC alloys for package-level applications. (May 4, 2009, Henkel Corporation) |
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Dual Channel Pulse Testing Simplifies RF Transistor Characterization Device engineers and test managers are under tremendous pressure to make sure products get to market quickly and perform reliably. This is especially true of RF transistors destined for hot communications market segments. Whether the technology is based on III-V compounds or LDMOS, RF transistor tests must accurately characterize design and performance and do it cost effectively. Pulse I-V (PIV) testing is becoming indispensable in meeting these goals, because it avoids the negative effects of self-heating and transient trapped charges, which usually result in misleading data. (In the testing of compound semiconductors, dispersion is the terminology used to describe self-heating and carrier trapping basically anything that causes DC test results to differ from pulse I-V test results.) (Apr 17, 2009, Keithley Instruments) |
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High Precision Ion Beam Milling with Time of Flight Compensation Advanced circuit editing (CE) becomes more and more difficult as semiconductor structures shrink. Time of Flight (ToF) compensation noticeably extends the utility of advanced CE for small geometries. ToF compensation in the ion-column deflection system increases beam placement accuracy and consequently pattern accuracy by reducing dwell times to as short as 50 nanoseconds. The authors of this paper have validated this approach through machining and filling 50-nm vias. Read the paper to learn how FIB operators can drastically shorten dwell times and pixel rates to improve gas milling and deposition activities. (Feb 11, 2009, FEI Company) |
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Backside Circuit Edit on Full-Thickness Silicon Devices Backside Circuit Edit (CE) techniques, in which a Focused Ion Beam (FIB) operator accesses critical circuitry through the substrate of an IC, are popular with processor manufacturers and users of FlipChip and BGA-style packages. However, the thinning, polishing and etching required for backside CE might make sample chips too fragile to withstand the electrical tests. This paper explores the use of backside CE on full-thickness silicon devices instead. It shows how modern IR camera technology combined with advances in silicon trenching, navigation and positioning can make the full-thickness approach very viable for the FIB operator. (Jan 22, 2009, FEI Company) |