Tom Adams from Sonoscan describes advances with "chip-in-polymer technology, developed at Germany's Fraunhofer IZM, which achieves 3D packaging advantages through better shock/vibration protection and shorter interconnect distances.
Presentations at this year's International Symposium on Microelectronics (IMAPS, San Jose, Nov. 1-5) included discussion of TSV/3D integration challenges and temporary bonding steps qualified for different process flows, and a wafer-level packaging (WLP) encapsulation process and stacked multi-chip package (MCP) for a MEMS variable capacitor and control IC chip.
Samsung Electronics has developed the world’s thinnest multi-die package, one that measures 0.6mm in height. Designed initially for 32 gigabyte (GB) densities, the new memory package is just half the thickness of a conventional memory package of eight stacked chips (or dies). The advanced packaging technology delivers a 40 percent thinner and lighter memory solution for high-density multimedia handsets and other mobile devices, according to the company.
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Photovoltaic Modules get a Charge from New Electrically Conductive Adhesives
For high reliability applications such as satellite, automotive, medical and telecom products, electrically conductive adhesives are often used as an alternative ... Sponsored By:
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Breakthrough Package-Level Lead-Free Alloy Addresses Board-Level Alloy Challenges
Not all SAC alloys are created equal: Especially when attempting to use board-level recommended SAC alloys for package-level applications.... Sponsored By:
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Die Attach So Smart it Knows Where to Go
Things in the semiconductor packaging world continue to get smaller and thinner, driving the need for materials to become smarter and more effective.... Sponsored By:
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How Low Can You Go?
Improvements to Low-temperature Curable Electrically Conductive Pastes Advance Touch Panel and LCD Applications... Sponsored By:
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