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Mar 24, 2010
In part two of the "It’s Time for 3D Now" webcast series, speakers from EMC-3D Consortium members Applied Materials, Semitool and EV Group will provide an update on their latest achievements in meeting the consortium’s expanded roadmap.
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Sep 17, 2009
The use of new packaging methods enables production of IC's with reduced cost, lower power consumption, small form factor, higher performance and increased yield and reliability. The realization of vertical interconnected devices or chips using Through-Silicon Vias (TSV's) is one of the key emerging trends in wafer level packaging. 3D integration can be seen as a paradigm shift of the semiconductor industry, which has improved device performances by shrinking gate dimensions according to Moore's Law. 3D integration, by exploiting the vertical dimension, provides an opportunity to continue to achieve the performance levels required by the extrapolation of Moore's law, but using a different technological approach ("More than Moore approach"). The rapid adoption of 3D integration technology seems to be essential as the industry paradigm is shifting to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D silicon-based technologies in highly integrated systems. The webcast will focus on the process integration, with speakers from market research and consultancy, industry and equipment side giving an update on the industrial 3D-IC landscape, user requirements and process challenges and solutions.
Sep 18, 2008
The wafer-level capping of fragile MEMS structures (e.g. for accelerometer, gyroscopes and pressure sensors) for protection and sealing purposes with wafer bonding is quickly displacing chip-scale packages. Especially for novel consumer MEMS applications (see the Apple iPhone or the Nintendo Wii) that have to keep record-small form factors, wafer bonding is a major contributor to reduce the manufacturing costs of the final package. New bonding schemes for "true" wafer-level-packages (protection, interconnection and testing at the wafer level) are being discussed with regards to market potential and equipment requirements.
The successful technology transfer of wafer bonding and related advanced manufacturing technologies from MEMS packaging into 3D wafer stacking of CMOS based applications (e.g. CIS packaging, DRAM stacking) will be another major topic of this webcast.
Jun 26, 2008
Convergence of front and back end process and technologies are driving successful high yielding examples of 3D devices to head into early markets. Continued success of 3D products relies on continued improvements across the 3D segments. Experts will address three of the key challenges to 3D implementation; TSVs, Bonding, and Thin Wafer Handling.
Apr 30, 2008
Electronics manufacturing is driven towards further integration and miniaturization. This process generates a need for improved manufacturing technologies for IC-based stacked modules. One method for improving the manufacture of 3D interconnection pattern technology is based on photo lithography for low cost miniaturization, cost reduction, and design freedom. Building the latest in new stacked components involves using processes that require precision imaging. This webinar covers lithography applications for 3D packaging by looking at image sensor packaging, and 3D lens printing. A user reviews which equipment can be used for lithography and use challenges for it. Presentations will be given from industry experts such as Dr. Michael Toepper from Fraunhofer IZM or Dr. Dietrich Toennies, Business Development Manager Mask Aligners at SUSS MicroTec. This webinar is critically important for engineers and management seeking practical information on lithography for use in 3D packaging.
Mar 25, 2008
Many socket manufacturer designs meet the needs of a wide range of customers. Test sockets must be able to survive a high-volume environment, producing high yields, excellent repeatability, and match an array of package formats. To match the exact interconnect solutions needed, some companies offer innovative custom designs. For high performance fine pitch 0.5mm QFN packages, sockets must be able to dissipate several watts without extra heat sinks. Today's sockets must accommodate the latest and more outdated IC package styles no matter the format - from BGA to QFN and many others. This webinar features a wide discussion of how to find, fit, and use the latest socket materials, designs, and resources by asking industry experts direct questions. For trends on where the industry is headed, an industry guru will forecast the numbers, revealing the forces behind each trend. Toward the end of the webinar, attendees may submit questions to the presenters. If you only attend one socket seminar this year, "Sockets That Meet Today's Needs" should be that important one.
Jan 17, 2008
3-dimensional (3D) packaging exploits the third or Z height dimension to offer a solution for higher integration and performance. Though one begins with known good die (KGD) and pre-tested packages, the reliability of the integrated package is determined using specific steps. Reliability assurance includes moisture resistance testing, autoclave, temperature/humidity, and at the board level thermal cycling. All of the tests that determine if the "whole" structure is sound are discussed in this important webinar. Experts discuss materials used to support multiple layers, such as underfill, solder balls, and interposers. Final test requires more than one tester and a design allowing access to all chips and packages through dense pin designs. Everyone involved in building 3D packages should attend this specific webinar, because even if you build a better integrated 3D package, reliability testing is proof that it will work.
Dec 11, 2007
3D packaging is experiencing high growth in new applications by delivering a high level of silicon integration and area efficiency at the lowest possible cost. Integrating off-the-shelf chips from different suppliers offers the function designer a high level of design flexibility at lower cost. But integrating chips with different process technologies (memory, MEMs, SiGe and CMOS) requires design strategies. It's not just whether you stack bare die and interconnect with flip chip or wire bonds, or stacking KGD and packages, or using a multiple package model, 3D packaging can be a challenge. This webinar focuses on how to design 3D packages of many types taking into consideration the materials and equipment needed to handle the process with speed and ease. It covers design rules and infrastructure needed for thinner substrates. Attendees include designers, project managers, and production engineers willing to look at the specific methods and materials needed to handle 3D integration.
Nov 30, 2007
This webinar covers the building blocks of MEMS processing, including deposition, photolithography, wet etching, reactive ion and deep reactive ion etching. Building a robust microelectromechanical system involves controlling each step carefully. Once the manufacturing process is under control, how can these small devices be tested for reliability? An expert in this area looks at techniques for studying material properties, electrical test systems and probe chambers, shock and vibration testing. Environmental testing from humidity through various pressure, temperature and gas variations gives assurance of reliability. Learning from leading industry experts on how to build better MEMS makes this webinar essential for those involved in all aspects of production.
Nov 15, 2007
OEMs are turning to 3D packaging to achieve a high level of functional integration in small form factor. The variety of technologies surrounding miniaturization and the need to cram more functionality into smaller devices has created a dilemma among packaging experts. This creates a lively discussion topic for leading packaging engineers from top firms to leading universities. Everyone wants to integrate an ever-increasing number of discrete products/functions into one device. But what format works best: IC integration to system-on-a-chip (SoC); 3D stacked die in chip scale packages in a system-in-package (SiP); or package-on-package with integrated logic and high-performance memory devices. A mix of memories, including Flash and DRAM, digital and RF analog chips or MEMS are the next steps in 3D. Some of these packaging styles fit certain applications best. Some control costs. Some are extremely costly to build. Some present a technological challenge. This webinar should be attended by package designers, board designers, packaging laboratories, OEMs and SATs providers who need answers to critical packaging problems.
