Users of WIN's GaAs foundry services can engage in wafer-level and package test in Silicon Valley, CA, and Grenoble, France.
Continental Corporation applied economic conveyor and handling modules from IPTE’s EasyLine product portfolio to link its gold and aluminum wire bonding, mounting, and AOI areas.
SRC and researchers from Georgia Tech made two advancements to meet key challenges facing off-chip interconnect solutions. The results address both the urgent need for greater off-chip bandwidth and reduced power per bit, and promise to enable continued improvements for system performance.
In this video interview, Sesha Varadarajan, Novellus, says that capacitance issues must be overcome, and the PVD step must provide good enough coverage to properly apply copper. CTE mismatch can also cause issues.
Assembléon’s recently released Twin Placement Robot (TPR) will reportedly reduce costs for semiconductor backend manufacturing. The TPR fits on Assembléon’s A-Series pick & place equipment for packaging and IC placement. Plans are in the works for the TPR to do semiconductor manufacturing tasks as well.
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The 5th annual IeRMCR Conference, September 21 in Loughborough, UK, will include 4 sessions: Advanced packaging, Materials processing and assembly, Printed electronics, and EPSRC.
KGD (Known Good Die) Packaging and Test Workshop 2010 will focus on semiconductor die products test, assembly, manufacturing, and business issues in the microelectronics industry. Bill Bottoms will keynote, covering deep submicron and 3D integration.
Peter Ramm, Fraunhofer EMFT, will be the Opening Speaker at the 7th Annual International Wafer-Level Packaging Conference (IWLPC). Ramm will present "The European 3D Technology Platform for Heterogeneous Systems" at the Kick-Off Reception.
Carsem is aggressively expanding its MLP/QFN package manufacturing capacity in Ipoh, Malaysia and Suzhou, China factory locations. This capacity expansion in assembly is matched with an equal proportion of test capacity expansion.
IXYS Corporation (NASDAQ:IXYS) integrated silicon carbide (SiC) technology and super junction MOSFET technology into a single package, enabling increased power density and higher efficiency in fast switching power supplies and solar inverter applications. The MKE product line is said to allow easier mechanical layouts and reduce parasitic losses over separate discrete package designs.
Dr. Phil Garrou gives his insight into leading edge developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more.
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Understanding Low Outgassing Adhesives
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