Bob Johnson, Gartner, tells senior technical editor Debra Vogler that the semiconductor industry is going into a period of slower growth. The result will be a flattening of equipment spending before the industry sees its next cyclical downturn in the 2013-2014 timeframe. 

Bill McClean explains why he does not see a double-dip recession on the horizon. He also comments on 450mm wafer semiconductor manufacturing (it will happen within the next 10 years).

Applied Materials (NASDAQ:AMAT) released Eterna, a new flowable CVD (FCVD) technology. Ajay Bhatnagar, director, global product management in the Gap Fill Dielectric Division, explains in-depth how it differs from conventional CVD. The technology is run on AMAT's Producer Eterna FCVD system. He also explains how it is being applied to new device architectures such as DRAM vertical transistors, NAND vertical bit stacks, and FinFETs.

Tom Gubiotti, product marketing manager at KLA-Tencor, discusses the design decisions that drove the company’s new film metrology tool -- the Aleris 8330 -- targeted for non-critical films at 32nm and below. Among the drivers -- especially for memory  manufacturers -- is the need for high-throughput, low cost-of-ownership tools that are capable of recipe sharing around the fab, so-called, “future proofing.”  Gubiotti speaks with senior technical editor Debra Vogler.

Adrian Kiermasz, Metryx, provides an update on the semiconductor manufacturing industry's upturn. Semiconductor makers are again placing orders to bring capacity higher. Metryx's product-wafer metrology is fast, with a lower cost than typical metrology systems.

Rob Rhoades, Entrepix, sees CMP being adapted for new purposes, beyond CMOS integration. TSVs are improving packaging, and CMP is one way to create them. Materials development and integration technology are needed to make these packages work. TSV is just one new application of CMP; others include epitaxial layers for LEDs.

Nick Colaneri, Flexible Display Center, talks about the Center's goal of developing and promoting flexible displays for the military and other applications. This requires a knowledge and incorporation of the latest equipment and materials from industry and academia, as well as a nod to the economics of processes.

Joe Cestari, Total Facility Solutions, sees opportunity in improvement to supply chain, to bring infrastructure into the picture with facilities and other investments. He sees large orders as exciting and yet daunting for many companies.

Tod Higinbotham, ATMI, says that a lot of new semiconductor materials need to be integrated, particularly at 22nm and beyond. The volume of materials requires investment in processing tools and research.

Geoff Irvine, SAFC Hitech, notes that the HB-LED market is growing at 30% over the next 5 years, particularly in Asia. Silicon semiconductor manufacturers are now moving into the LED sector.

Mark Allison, Verigy Ltd., points out that the economic downturn helped promote the outsourced semiconductor assembly and test (OSAT) model, which pushes test platforms into more configurable models.

Bob MacKnight, Crossing Automation, points to the future of Crossing Automation now with the acquisition of Asyst Corporation. Combining vacuum and atmospheric components offers platform automation from end-to-end in the semiconductor manufacturing Tier II and Tier III companies. Automation faces issues with single-wafer sorting, floor-space management, and shifting business models, among other elements.

Bob Hollands, ASM America, offers insights from a strong, active SEMICON West. He discusses the company's work on high-k, with several companies in the semiconductor manufacturing market moving to mainstream high-k. Scaling 22nm is still a challenge, and Hollands sees this as a gate-last technology.

Stuart Riley, Value-Added Software Solutions, discusses a way to monitor quality control based on die data, rather than wafer-based data. He discusses how this data is grouped and analyzed for different fab models.

Ralph Spicer, Qcept Technologies, describes technology for detecting discontinuities in the workfunction at the surface of wafers -- such discontinuities cause non-visual defects (NVDs). NVDs are primarily surface chemical defects caused by organic and metallic residues and process induced charge. Because NVDs do not scatter light, they are not detectable by optical inspection tools. Based on the well known principle of contact potential difference (the actual probe does not contact the wafer), the Qcept method detects sub-monolayer contaminants -- at the millivolt level -- that can impact device performance (Figs. 1-2). As the number of new materials increases at advanced semiconductor manufacturing nodes concurrent with shrinking process windows, it is becoming increasingly critical to detect NVDs.

Pol Marchal, principal scientist, 3D-SoC Design Initiative at Imec, discusses why the consortium has the TSV process under control and provides insight into global mechanical stress -- a problem that still remains to be solved for 3D stacking schemes. Marchal also identifies key specifications for TSV technology that is to be used for mobile devices.

Kurt Ronse, director of Imec's advanced lithography program, describes the consortium's "round robin" EUV mask inspection review process and summarizes EUV resist results to date. The recording took place during Imec's Technology Forum Press Gathering (July 7-8) in Belgium.

Roger Grace, President of Roger Grace Associates, explains why he views HP's seismic platform as groundbreaking technology. The new accelerometer will be used in a distributed autonomous wireless network. The marketing consultant tells Sr. Technical Editor, Debra Vogler, that HP is creating a total solution that will revolutionize oil and gas exploration, as well as enable infrastructure monitoring, airplane monitoring, and so forth.

Jeffrey Perkins, President of Yole Inc., discusses the trends in MEMS manufacturing and packaging with Sr. Technical Editor, Debra Vogler. Perkins noted in his presentation that integrated MEMS market share is still marginal and only motivated by high volumes. He explains how this will change going forward.

Janusz Bryzek, CEO of Jyve and MEPTEC MEMS Symposium co-chair, discusses the market opportunities and the benefits of standardization of MEMS processes with Sr. Technical Editor, Debra Vogler. The growth of MEMS integration with ICs is enabling consumer, industrial, aerospace, and medical markets in the billions of units - with growth projected to trillions of units over the next 10 years. Bryzek also speaks about the benefits of standardization of MEMS process technologies.

Mike Armacost, 2010 IEEE IITC Publicity Chair (and managing director at Applied Materials), outlines papers on emerging memory technologies, new features, and newer technologies for SST Sr. Technical Editor, Debra Vogler. In particular, Samsung will be presenting a paper on gap fill using SOG material. And IMEC will present a spacer-defined double-patterning technique on a 20nm hp structure. Fujitsu will present a paper on interconnects for graphene in which a carbon-based material is deposited in order to grow a network of nanographic wires on a dielectric.

Mike Shapiro, 2010 IEEE IITC General Co-chair (and chief technologist, 3D development at IBM) tells SST Sr. Technical Editor, Debra Vogler, about the explosion of papers on 3D at this year's conference. The topics covered are at a higher level too, with processing and materials pushing the limits of fabrication, according to Shapiro. There will be a group of papers that highlight advances in characterization, three papers on advanced joining techniques, and papers that cover the use of 3D by the fabless semiconductor sector. 

John Iacoponi, 2010 IEEE IITC North American Program Chair (as well as technology research manager at Globalfoundries) outlines key focus areas at the conference this year. He tells SST Sr. Technical Editor, Debra Vogler, that the three key areas are: metallization, the emergence of back-end memory technologies, and the growing importance of 3D interconnect technology. With respect to metallization, Iacoponi notes that there is no convergence on any single barrier seed technology at the 32/28nm node. "Everyone is trying to extend incumbent PVD technologies," notes Iacoponi. In particular, there will be papers on self-forming barriers and CVD barriers.

In a podast interview at The ConFab with SST's Debra Vogler, Aart DeGeus, chairman/CEO of Synopsys, puts the economic recovery into context for the semiconductor industry, where the growth driver is shifting from scale complexity to systemic complexity, with many more inputs and everything working correctly.

Hans Stork, CTO & Group VP, at Applied Materials, tells Sr. Technical Editor, Debra Vogler, how a number of new inflection points are driving technology today. Equipment suppliers have to focus on obtaining greater efficiency with a maximum return on effort and providing the fastest path to production. Once a new technology is proven, end users demand higher productivity and lower CoO. To keep new technology ideas going forward, Stork notes that collaboration between partners has to transcend new boundaries; he describes one example of current work at the company.

Peter Jenkins, VP of Marketing at ASML, puts the deployment of EUV into perspective. He tells SST Sr. Technical Editor, Debra Vogler, that EUV's extendibility will enable Moore's Law for multiple generations - down to well below 10nm. The company expects it can intersect different end user roadmaps and specific applications along the way. Jenkins also describes the cycles of learning needed for reticles and resists.

Peter Rickert, TI Fellow and Platform Director, explains to SST senior technical editor Debra Vogler how a paradigm shift in SoC design has caused designers to move higher up the food chain. For example, at 40nm, SoCs have around 50-100M gates and bits of memory, so TI is coupling three areas to address power issues and enable differentiation of its products. Providing hooks in the design ensures better management of power.

Economics of 3D ICs session leader, Sitaram Arkalgud, Director, 3D Interconnect Division at SEMATECH, describes for Sr. Technical Editor,  Debra Vogler, some of the possible ways to reduce the manufacturing cost of 3D ICs, particularly TSVs. For example, the bonding process would benefit from cost-reducing efforts as well as RDLs. Arkalgud also suggests that standards for bonding and assignment of TSV locations in lieu of customized solutions would be useful.

Bryan Rice, Director of Lithography at SEMATECH, summarizes the survey responses from 131 of the more than 180 attendees of its Litho Forum (5/10-12/10). Of particular note, respondents believe that if there is a limitation to lithography, it will occur at, or below, 8nm in critical feature size. Though EUV remains the dominant choice in lithography technology to carry the industry forward, a significant number of responses indicated that direct write and direct self-assembly are two technologies worthy of continued investment.

Stefan Wurm, Associate Director of Lithography at SEMATECH, summarizes the discussion at SEMATECH's Litho Forum (May 10-12, 2010). He tells Sr. Technical Editor, Debra Vogler, that fabless companies are looking for a different way to engage with foundries. And equipment suppliers still need solutions to R&D funding for new tool development as well as the transition to 450mm manufacturing. IDMs are coming up with different solutions that are very specific to their needs. It is hoped that discussion at the conference will shed light on a consortia model for cost-sharing.

Ana Hunter, VP foundry, at Samsung Semiconductors, discussed the company’s process technology roadmap and foundry strategy at its Thinnovation media and analyst event on April 7, 2010 in San Jose, CA. Hunter tells Sr. Technical Editor Debra Vogler about HK+MG developments to be rolled out later this year at 32nm and the company’s plan for scaling it to 22/20nm.

Joel Barnett, a senior member of the technical staff at SEMATECH and chair of SEMATECH’s Surface Preparation and Cleaning Conference (3/22-24/10), summarizes the panel discussion on all wet photoresist stripping. The need is being fueled by reliability challenges (e.g., pinholes) that accompany the use of new materials at advanced nodes. Barnett also addresses EUV resists.

SEMATECH president & CEO, Dan Armbrust, discussed the highlights of his keynote address at SEMATECH’s Surface Preparation and Cleaning Conference (March 22-24, 2010) with Sr. Technical Editor, Debra Vogler. The topic of his address was creative collaboration and how it has changed in the industry. Key drivers of changes include industry consolidation, which brings a greater need to share risk among companies that are increasingly specialized, as well as government funding of ESH and green technologies, and ever more complicated technical challenges that single companies alone cannot solve.

Jimmy Price, a member of the technical staff at SEMATECH and a presenter at SEMATECH’s Surface Preparation and Cleaning Conference held the week of March 22, 2010, describes the technical challenges associated with metrology and characterization methods that do not transfer from silicon to III-V materials. Finding such characterization methods is critical because compound semiconductor materials are being evaluated as a way to introduce higher mobility channels at advanced nodes. Results of one technology that could be used with III-Vs, second harmonic generation (SHG), are discussed by Price.

Aki Fujimura, President & CEO of D2S (the company is a managing sponsor of the eBeam Initiative, www.ebeam.org), speaking at ISQED 2010 (San Jose, CA), continued making the case for design for eBeam (DFEB) mask technology. In this podcast, Fujimura tells SST Sr. Technical Editor, Debra Vogler, what is involved with using one-shot character projection direct write eBeam methodology and how coordinating standard cells in the design phase with stencils available in the fab is critical to success.

ISQED Conference Chair, Pallab Chatterjee, also of Silicon Map, describes the need for using field solvers to achieve higher accuracy needed for extraction at the 32/28nm nodes and beyond. This topic was explored in depth during the conference as part of a joint tutorial session conducted by Mentor Graphics and STMicroelectronics, as well as a presentation by Silicon Frontline. Another popular topic at the conference was the structured design use of test, i.e., making designs fully aware through power, through clock gating, etc., so that power design, performance design, and test are design criteria. 

Speaking at Semico Research Corp.'s Outlook event (March 2, 2010, San Jose, CA), Semico president Jim Feldhan discusses Semico's latest forecast for 24% growth in semiconductor revenue in 2010.

Keynote speaker Wally Rhines, chairman and CEO of Mentor Graphics, describes how the industry has, time and again, emerged from recessions with new products, driven by the need to innovate at ever lower price points.

Joanne Itow, Semico's managing director, summarizes her thoughts on fabs' challenges in dealing with a much broader array of products and technologies, specifically pointing to comments made by panelist and IBM Fellow, James Kahle.

Christian Wagner, Director Product Management EUV at ASML, tells SST Sr. Technical Editor, Debra Vogler, how the company anticipates the layer by layer insertion of EUV into production.

Applied Materials CTO, Hans Stork, discusses how self-aligned double-patterning can overcome the challenges of LELE. He also tells SST Sr. Technical Editor, Debra Vogler, about the successful joint project with Global Foundries to evaluate E-beam mask inspection for EUV. EBMI data was presented by Global Foundries' Obert Wood at Applied's annual Technical Symposium at SPIE.

Kurt Ronse, Program Director, Advanced Lithography at IMEC, updates SST Sr. Technical Editor, Debra Vogler, about the consortium's progress in extending 193i double-patterning, in particular, putting emphasis on keeping the process in the center of the window. He also describes IMEC's efforts to develop PORs for mask cleaning in the fab and correlating mask defects.

Mark Melliar-Smith, CEO of Molecular Imprints, Inc., answers the question: why imprint lithograpy for CMOS. He also discusses data presented by SEMATECH at the 2010 SPIE Advanced Lithography Conference for 11nm lines and spaces with high quality LER.

Carlton Washburn, Technical Product Manager at Brewer Science, gives SST Sr. Technical Editor, Debra Vogler, an update on DBARCs. He notes that at the 32nm node, a paradigm shift occurred, whereby implant layers moved from being non-critical to being critical.

SEMATECH's Director of Lithography, Bryan Rice, tells SST's Sr. Technical Editor, Debra Vogler, that the consortium has rallied the industry to address EUV mask blank infrastructure issues. "EUV mask infrastructure will be ready to support EUV insertion on time in 2013," said Rice.

James Carriere, Sr. Optical Engineer at Tessera, discusses increasing process windows with SMO and customized free-form illumination sources with SST Sr. Technical Editor, Debra Vogler. He also describes tunable DOEs and how they can be used to create hybrid patterns.

George Barclay, R&D Director, Lithography Materials, at Dow Chemical Company, discusses the company's thermal cure solution for achieving low CoO and robust process windows with SST Sr. Technical Editor, Debra Vogler.

EUV source challenges being tackled by Gigaphoton include high power driver laser stabilization and debris mitigation for longer collector mirror lifetime. GM Tatsuo Enami, also told SST Sr. Technical Editor, Debra Vogler, that the company is currently designing a CO2 laser system in house that is optimized to the LPP EUV light source. Features include gain profile and resonator design optimization, the introduction of adaptive optics to compensate for the thermal deformation of mirrors and windows, and high thermal load optics improvement. Debris mitigation is being accomplished by a combination of using a mass-limited target, magnetic mitigation enhancement by pre-pulse heating, and Sn cleaning technology. The company is projecting shipments of its excimer light sources in 1Q10 that will match shipment levels for all of 2009.

EUV is gaining momentum, but realisticallly, Franklin Kalk, EVP & CTO of Toppan Photomasks, sees the mask infrastructure not being completely ready until about 2015. He also discusses the ramifications of using DPT immersion litho in combination with EUV (cut mask) - an option put forth by Intel's Yan Borodovsky during the SPIE Advanced Lithography Conference.