Archive for '2013'

Join The ConFab discussion

February 26, 2013 11:27 AM by Pete Singer

The ConFab is Solid State Technology's annual conference and networking event. This year, it will be held June 23-26 at The Encore at The Wynn in Las Vegas. We recently started a LinkedIn group , where we will inform members of new activities, and keep the discussion going on topics related to semiconductor manufacturing, design, packaging and testing. Everyone is welcome to join .

The overall theme of this year’s conference is “Filling the fabs of the future,” with a focus on the types of products that will drive demand for semiconductors in the next decade, the technologies and processes that will be required to meet this demand, and the manufacturing and operational challenges that will arise as a result of this demand and how to meet them.

We’ll kick things off on Tuesday morning with a keynote talk by Yoonwoo Lee, executive advisor (and former CEO) of Samsung Electronics. He will speak on “Technologies and Business Strategies of the Future IT Industry .” Mr. Lee is well known for his accomplishments in pioneering the development of the memory chip and LCD industries in Korea, and has been widely credited for turning Samsung Electronics into a global leader in the semiconductor business.
Session 1 will focus on major economic trends, with talks from Jim Feldhan of Semico, Bill McClean of IC Insights, Mark Thirsk of Linx Consulting and Dan Hutcheson of VLSI Research.

Next, we’ll look at the design/manufacturing/packaging/testing supply chain, including collaboration between fabless/product design companies and foundries. Mike Campbell of Qualcomm and Jae Cho of Xilinx will present in this session.

In the afternoon on Monday, we’ll hear from a panel of experts on 3D integration, including Mike Ma of SiliconWare, Subu Iyer of IBM (who will also be keynoting on Tuesday morning), HoMing Tong of ASE, and Bob Patti of Terazzon. A special thanks to Phil Garrou and IEEE CPMT, the technical sponsor of this session and another session on Advanced Packaging.

Tuesday will begin with a keynote from Subu Iyer, followed by a panel session moderated by Scott Jones of Alix Partners. The session will focus on R&D Portfolio Management and Improving R&D Efficiency. Jones will share the results of a AlixPartners’ study of the 72 largest semiconductor companies globally over the past six years that found that companies with a higher degree of R&D efficiency show greater profitability.

We’ll then get into a status report on advanced packaging, with an excellent line-up of speakers, including: Devan Iyer from Texas Instruments, Bob Lanzone from Amkor, Steve Anderson from STATS ChipPAC, and Ted Tessier from FlipChip International.

In the afternoon on Tuesday, we’ll hear from Sanjay Rajguru of ISMI and a panel if speakers assembled by ISMI, focusing on accelerating manufacturing productivity.

We're posting information on the site about the speakers and their talks as we get them. Check it out!

Questions and answers on FD-SOI

January 4, 2013 2:56 PM by Pete Singer

A month or so ago, we implemented (without much fanfare) the ability to comment and rank articles on this site, and more easily use social media tools. I’d like to call your attention to one interesting exchange, and also invite you to start posting comments of your own.


In mid-December, we posted an article titled “STMicro: 28nm FD-SOI is ready for manufacturing ” which elicited an interesting comment and response. The story noted that ST’s "feature-complete and silicon-verified" 28nm planar FD-SOI Technology Platform, which is now open for preproduction from the Crolles 300mm manufacturing facility, encompasses a full set of foundation libraries (std-cells, memory generators, I/Os, AMS IPs, and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices. Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform revealed a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, according to Jean-Marc Chery, EVP/GM, digital sector, and CTO/chief manufacturing officer of STMicroelectronics.

Sang Kim first commented, noting that “IBM had developed FD-SOI technology for the first time, but was not successful in manufacturing up to now because of the following four main reasons: Floating body effect, self-heating, ultra-thin SOI approximately 7nm required for 28nm node, and high SOI wafer costs.” Kim noted that STMicro didn’t mention how it has resolved these four problems.

In response, STMicro’s Giorgio Cesana, director of technology marketing, posted a follow-on comment that I thought was quite interesting. Here’s what he said:

“Thank you for those comprehensive questions. Responding gives us a chance to provide details of the advances of UTBB FD-SOI technology and remove any doubts you may still have about it.

1. Ultra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect. In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

2. Self-heating is also a problem that exists with partially-depleted SOI technologies, where the buried oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects. UTBB FD-SOI technology offers two advantages to overcome this self-heating: The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance; The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

3. Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

4. Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

We hope these answers convince you, as they’ve convinced us, of the suitability of FD-SOI technology for sub30nm semiconductor manufacturing.”

Thanks for the comments, and stay tuned for more of FD-SOI.