IFTLE 135 UMC / SCP Memory on Logic; SEMI Europe 3D Summit part 2
UMC/STATSChipPAC
UMC and STATS ChipPAC (SCP) have announced a jointly developed TSV-enabled 3D IC chip stack consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip. This was developed under open ecosystem collaboration using UMC’s foundry capability and STATS ChipPAC’s packaging capabilities. Representatives of UMC and SCP both declined to indicate where the memory came from, but did say that they were working with customers to commercialize this product.
Xilinx
Suresh Ramalingam, Sr Dir of Adv. Packaging shared a nice slide on the CoWoS TSMC process being used to fab their Virtex-7 2000T FPGAs.
Brandon Wang, Director 3D IC and Advanced Technology Product Management
for Cadence gave us the latest IBIS take on the costs incurred at the latest nodes,
and their short, medium and long term look at TSV application space.
SSEC
Laura Mauer of SSEC compared post grind TSV reveal options noting that KOH etches Si at 3-4X the reate of TMAH without touching SiO2 or copper.
Dave Butler of SPTS also addressed the via reveal step. Dave contends that “standard” low temp TEOPS oxide is unstable over time absorbing water and showing increases in electrical leakage and refractive index changes. They recommend their “stable” LT TEOS oxide which they claim shows no drift in electrical properties, no changes in stress and no water absorption over time.
They also recommend using SiN as an etch stop layer to get up to 30% higher throughput.
UMC and STATS ChipPAC (SCP) have announced a jointly developed TSV-enabled 3D IC chip stack consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip. This was developed under open ecosystem collaboration using UMC’s foundry capability and STATS ChipPAC’s packaging capabilities. Representatives of UMC and SCP both declined to indicate where the memory came from, but did say that they were working with customers to commercialize this product.
Continuing our look at the European SEMI 3D Summit:
Xilinx
Suresh Ramalingam, Sr Dir of Adv. Packaging shared a nice slide on the CoWoS TSMC process being used to fab their Virtex-7 2000T FPGAs.
Cadence
Brandon Wang, Director 3D IC and Advanced Technology Product Management
for Cadence gave us the latest IBIS take on the costs incurred at the latest nodes,
and their short, medium and long term look at TSV application space.
Laura Mauer of SSEC compared post grind TSV reveal options noting that KOH etches Si at 3-4X the reate of TMAH without touching SiO2 or copper.
SPTS
Dave Butler of SPTS also addressed the via reveal step. Dave contends that “standard” low temp TEOPS oxide is unstable over time absorbing water and showing increases in electrical leakage and refractive index changes. They recommend their “stable” LT TEOS oxide which they claim shows no drift in electrical properties, no changes in stress and no water absorption over time.
They also recommend using SiN as an etch stop layer to get up to 30% higher throughput.
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