Perofessor Takeuchi of Chuo Univ described a hybrid SSD architecture using ReRAM and high capacity NAND flash memory.
When SSDs are used for servers in financial institutions, performance is hindered and power consumption increased because random access is dominant. This causes data to get split up if the size of the data packets are not of the appropriate size (minimum for NAND is 16Kb). Takeuchi's memory stack combines a NAND flash memory and ReRAM. ReRAM is used as both cache and storage memories. To overwrite a small amount of data in the NAND flash memory, software transfers the page of data to the ReRAM so that data is not fragmented in the NAND flash memory.
(Click on any of the images below to enlarge.)
A prototype, tested on an emulator, showed that compared with existing SSDs which only use NAND, the hybrid memory stack achieves an 11X higher data writing performance, 93% lower power consumption and 6.9 times longer product life. This assumed that the controller, ReRAM and NAND flash memory were connected by TSV. Although this has been hyped up by several reporters, we should note that it is possible to achieve almost the same results without using TSV. The major gain of using the TSV appears to be a 14% decrease in energy required to write as shown in the comparative table below.
It is proposed that SSD in data centers would have to be changed out about 7 times less thus reducing expenses.
It should be noted that in order to use the hybrid SSD architecture for different applications, it is necessary to change the controlling software algorithms.
The HMC is a stack of multiple thinned memory die sitting atop a logic chip bonded together using TSV. This greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs. The HMC requires about 10% of the volume of a DDR3 memory module. It is claimed that the technology provides 15X the performance of a DDR3 module, uses 70% less energy per bit than DDR3 and uses 90% less space than today's RDIMMs. [see IFTLE 95 "3DIC - Time Flies When You're Having Fun; Further Details on theMicron HMC..."; IFTLE 74 "The Micron Memory Cube consortium"]
The HMC device uses TSV technology and fine pitch copper pillar interconnect. The DRAM logic, responsible for DRAM sequencing, refresh, data routing and error correction is placed in a separate high performance logic die. DRAM and logic are connected by thousands of TSV. The DRAM is a slave to the logic layer timing control. The HMC was constructed with 1866 TSVs on a roughly 60um pitch.
TI Studies Impact of TSV Stress on Electrical Performance