As Jack Nicholson said in the great Stephen King horror classic “The Shining”
Wanting to keep you up to date with recent activities, and yet not loose any of the materials that were in que two months ago when Semiconductor International went under, I will present a quick summary of announcements and rumors at the 2010 ECTC in this blog and follow with some of the blogs that were in que. I will then continue with discussions of key presentations from ECTC which should carry us into mid July and Semicon West.
They say “What goes on in Vegas stays in Vegas
”. Not so when we’re talking about 3D IC and advanced packagingâ¦that gets reported here in IFTLE.
IEEE CPMT Takes Over Full Sponsorship of ECTC
The ECTC Conference in one form or another has been in existence since 1950. The joint sponsorship by the IEEE Components, Packaging and Manufacturing Society (CPMT) and the ECA (formerly the EIA) ended last week when IEEE bought out their long time partner. Rolf Aschenbrenner, President of IEEE CPMT commented that “.. this change should be invisible to the attendees and the ECTC program committee. We plan no changes in how the ECTC operates”
[ top l to r: Tom Reynolds, Bob Willis , Rolf Aschenbrenner,
CP Wong, Steve Bezuk, bot: Marsha Tickman, Jean Trewhella, Bill Chen ]
Fan Out WLP taking off
Most of you are familiar with fan out packaging which was developed in parallel, several years back, at Freescale
(RCP) and Infineon
(eWLB). During the recent hard economic times Freescale scaled back their process work and eventually licensed their process to Nepes
. Infineon developed a commercialization consortium with ST Micro
and most recently Nanium
(formerly Quimonda Portugal). eWLB wafers have been in mass production on 200mm lines at Infineon, ASE and STATS ChipPAC since 2009. STATS has been aggressively pursuing commercialization [ highlights from the 2010 ECTC
] . STATS and Nanium are in the process of scaling up 300 mm lines. SPIL
and others are also developing their own Fan-out wafer level packaging options.
The STATS team is pictured below at their ECTC booth where their eWLB technology was highlighted.
[from l to r: Vic Lozada, Raj Pendse, Flynn Carson, Lisa Lavin and Seung Wook Yoon]
Rumors are circulating that Freescale management, seeing the success that eWLB has been receiving, has revived their RCP process group and are looking to obtain further licenses. Rumors are that Broadcom is looking seriously at the RCP based devices. Talking with STATS who claims yields “..are already in the 90’s” for the 5-10MM units they produced in Q1 2010, it became clear that the reconfiguration step is not as simple as it looks on a power point slide. Molding compound shrinkage requires that the chips be unequally spaced across the wafer before molding compound is applied and cured and the subsequent RDL mask must match this unequal spacing – obviously. Multi die eWLB (i.e SiP ) have been qualified by the STATS team who now have stacked, (two sided) eWLB solutions in development. In any event, fan out WLP has officially taken off and will unquestionably become a major packaging option in the future.
Global Technology Development Focus Remains on 3D IC
I counted more than 25 presentations involving TSV based 3D IC. Although there were no commercial announcements, there was continued steady progress by nearly all the major players in the industry. By the way, I’m seeing more and more use of the acronym 3DIC so when doing lit searches you better use both.
I saw nothing to change my mind that the industry has narrowed process options down to vias middle (from the foundry) and vias last backside (from the OSATS). The latter mainly for devices such as CMOS image sensors which are already in full commercial production at players such as Toshiba, ST Micro and Samsung.
You can be sure that not having a source of chips with vias middle TSV is slowing down product development work. Currently, only those with their own IC fabs can gets chips containing built in TSV. While everyone is awaiting TSMC, Global Foundries and others, there appears to be a significant opportunity for R&D IC lines that can deliver test chips with vias middle TSV for developers to work with. IMEC has shown this capability, but who else out there can make such structures available ??
Please send me your info if you are or could be supporting this need.
ASE focus on 3D IC
It appears that with Cu wire bonding completely installed at ASE they can now focus on 3D IC. I’m told the EE Times article indicating that 3D at ASE was imminent [ASE Breaks Ground on New Packaging Plant] stirred significant activity at the ASE sales offices . Reports to IFTLE indicate that the new building in Kaohsiung (K 15) will indeed be used to bring all 3D equipment together, under one roof. Current D2D and D2W assembly from Chung Lee will be moved to Kaohsiung. BUTâ¦.I’m also told by those who should know, there will be no 300 mm 3D instillations till 2011 so commercial 3DIC assembly is unlikely before 2012, if then.
IBM 3D rumors
Last December at the RTI ASIP in Burlingame, IBM confirmed that there was no commercial qualified 3D line running yet. Speculation at the ECTC was that a TSV containing product will be introduced into their server line. Product would come off the R&D line. An announcement will come if performance meets expectations.
Recent announcements of their open innovation platform indicates that TSMC is putting the pieces together to enable 3D design [TSMC adds 3D, ESL tp Platform Efforts]. Their design plans will first deal with Si interposers and it will subsequently support full 3D stacking capability. IFTLE conversations with TSMC personnel indicate that their initial roadmap announcements showing vias middle in 2011 was (as PFTLE had predicted) extremely aggressive . They view silicon interposers as a faster solution for their graphics chip customers and will switch them to full 3D stacking later. The fact that long time TSMC partner ASE will not have 300 mm equipment in place till 2011 confirms this conclusion.
3D IC Bonding
There were 10 papers at ECTC dealing with various aspects of Cu-Cu and Cu-Sn-Cu bonding including papers from IMEC, IBM, Leti, Samsung, RTI, Univ Tokyo, Nanyang Univ, / Globalfoundries. As PFTLE noted many years ago, the low COO choice of bonding techology will be limited to choices that result in mechanical and electrical connection at the same time. While the OSATS have been focused on developing Cu/Sn intermetallic technology for 3D strata bonding, there is still significant commercial interest in copper-copper bonding, perhaps due to the lower resistance connections. Cu-Cu bonding comes in white or black i.e. thermocompression or direct bonding. Actually there is enough data out there now that is becoming evident that a continuum exists between the two – shades of grey -which are dependent on the variables of surface finish, temp and pressure. A full blog will be coming up in a few weeks discussing all of this information.
Thin Film Dielectrics
Michael Toepper, Fraunhoffer IZM dielectric expert, discussed thin film polymers to a standing room only crowd and concluded that materials with the highest tensile strength and elongation were best suited for reliable fan in and fan out WLP structures.
Fan out WLP require lower temp curing materials since the chips are embedded in low temperature molding compounds. Most of the practitioners IFTLE is aware of are using JSR ( WPR 5100 series ) which are epoxy novolacs with rubber filler or the new HD Micro low cure temp PBOs ( HD 8900 series ).
The Asahi Glass group (AGC) has focused application work for their ALX polymer on fan in and fan out WLP. This material is in trials at IME, IZM and RTI and looks very promising as a BCB substitute with double the elongation and curing at 190 â¦C.
[Hijiri Kuriyama, Alan Huffman (RTI), IFTLE, Takeshi Eraguchi ]
Coming up soon:
- Finding the Beef and Addressing 3D IC
- Sematech Addresses 3D Stress
- A Date in Dresden
For all the latest on advanced packaging and 3D IC stay linked to Insights From the Leading Edgeâ¦â¦â¦â¦â¦â¦â¦..