Archive for '2010'

IFTLE 29 IEEE 3D IC Test Workshop Part 2

December 22, 2010 3:18 PM by Garrou

Continuing with our discussions on presentations made at the 1st IEEE 3D IC Workshop in Austin.


NC State – TSV Test prior to stack


During wafer test, it is valuable to be able to determine which TSVs are likely to yield when used, and which are not. To detect failure in TSVs, an electrical test needs to be performed before 3D integration and chip packaging. Paul Franzon and co-workers at NC State propose three methods to test Through-Silicon-Vias (TSV) electrically prior to 3D integration: (1) sense amplification; (2) leakage current monitor; and (3) capacitance bridge methods. These tests detect one or both of two failure types, pin-holes and voids. The test circuits measure capacitance and leakage current of the TSVs, and generate 1 bit pass/fail signal. All these methods can be implemented for test-before-stacking, to attempt to increase assembled yield.


The sense amplification and the capacitive bridge test structures can estimate the TSV capacitance to test void defects. The capacitive bridge circuit is more sensitive but consumes more area than the sense amplifier sensor. The sense amplification method cannot detect voids isolating less than approximately ±10% of the TSV. The potential test escape rate is proportional to what percentage of TSVs that have voids isolating 10% of the TSV capacitance or less. The leakage current test circuit can measure the resistance of dielectric layer to test leakage defects with much more sensitivity than the sense amplifier method. All the simulation results above show that the parameters of TSVs can be tested by simple circuits and the measurement data can be streamed out serially by a scan chain.


TSMC – Electrical Tests for 3D IC with TSV


Chen and co-workers at TSMC have identified five main categories of “faults” (i.e. performance failure modes) in 3DIC TSV with microbumps:
1. Faults due to miss-alignment
2. Faults in the Cu pillar
3. Faults due to impurities
4. Faults due to substrate
5. Faults in the microbump


In terms of alignment, they report two possible failure issues. The type 1 failure is due to an alignment shift which results in smaller overlap area contact and thus higher resistance. The type 2 failure occurs when there is severe miss alignment and a complete open occurs.


The second category is related to the Cu TSV. Type 3 failures come from voids in the Cu TSV which may be caused by electromigration. The resistance in the TSV becomes larger and the RC delay increases. Type 4 failure occurs due to breakage in the TSV by improper handling or other procesing issues and will result in an open circuit. The type 5 failure is due to failure to completely fill the TSV. This will also increase delay due to the higher resistance.


The third failure mode is due to impurities during processing. Type 6 failure is due to impurities between the TSV and the microbump which increase the contact resistenace and thus the signal delay time. Type 7 failure is due to impurities between the microbumps which also increases the contact resistance and thus the signal delay.


The fourth and fifth failure modes deal with failures in the substrate and failures in the microbump. Type 8 failure is due to non uniformity in the insulation liner which can result in a leakage path from the TSV to the substrate. Type 9 failure results in an open circuit from Cu TSV delamination from the substrate due to the thermal stress of the process. Type 10 failure is due to deformation of the microbumps or the wafer warping and the separation of the two microbumps causing discontinuity. Type 11 failure is due to shorts between the two microbumps.


The Table below compiles failure modes vs required testing which includes continuity, resistance, capacitance, leakage and high frequency performance







Test structures are integrated into the 3D IC test flow as shown below:



TSMC reports that besides testing, thermal issues, electromigration, stress sensor, redundancy and ESD are still waiting to be solved.



Qualcomm


In a presentation covering DFT (design for test) Qualcomms Michael Laisne concludes that there are two primary defect classes: a) interconnect related defects and b) stress related defects. Either of which could manifest itself as a “stuck-at” or speed-related failure. He lists the main causes of interconnect-related defects as:


- substrate to TSV shorts,
- parasitic capacitance or resistance between the substrate and TSV causing speed-related failure,
- capacitive coupling between adjacent TSV causing both static and at-speed failures
- microbump opens and shorts, especially due to excessive warpage (opens) and misalignment (shorts)
- shorts due to interactions with TSV’s
- shorts and opens in the RDL


ST Ericsson


Stephane Lecomte of ST Ericsson reports that the first 3D TSV application they foresee in cell phones is wide IO memory which is currently undergoing JEDEC standardization. We have recently reported on similar conclusions from Nokia [see IFTLE 19,”Semicon Taiwan 3D Forum Part 2” ]


Most of the manufacturing issues, they feel are still tied up in the business model / infrastructure / supply chain issues that have yet to be resolved. They feel that boundary scan testing will be defined within JEDEC, but that BIST remains very manufacturer dependent.






ARM


ARM presented an interesting slide depicting the Mb/sec requirements for several common devices (shown below)






Certainly we would all agree that 3D IC test has come a long way over the last few years. All of the major design and test companies are now focused on integrating products so that full 3D IC integration can become a reality in the near future. For those worried that 3D still looks like it is many years away, I refer you back to the Qualcomm presentations that indicate that first generation products do not appear to have significant roadblocks in either thermal, design or test. It is for the future generation partially or fully reconfigured structures that major changes in design and test will be needed [ see IFTLE 9, “3D in and Around the Moscone”



Lastly…..One of the IEEE 3D Test Conference chairs requested that IFTLE model their midnight black knit shirt, so below we find our “mature” model showing off his shirt while reading the New York Times # 1 non fiction best seller “Handbook of 3D Integration” by Garrou, Bower and Ramm, available at Amazon.com !











……..Merry Christmas and Happy Holiday season to all our IFTLE Readers……..



For all the latest in 3D IC and advanced packaging in 2011 and beyond, stay linked to IFTLE……..






IFTLE 28 Testing 3D ICs Deep in the Heart of Texas

December 17, 2010 4:59 PM by Garrou

We have been discussing test as a significant issue for the commercialization of 3D IC technology for a few years now [see for example PFTLE 108 ” 3DIC Test ”, PFTLE 102 “ The Four Horseman of 3-D IC Integration ”, PFTLE 100, “ 3D IC in the City by the Bay “,IFTLE 13 “ 3D In and Around the Moscone part 3 ” , IFTLE 5, “ 2010 DATE in Dresden ”


The IEEE Int Test Conference (ITC) held in Austin in November had a full-day tutorial, several technical papers, and a panel session, all on 3D-TEST. This was followed by a dedicated 3D-TEST Workshop, the first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits “3D-TEST” which was chaired by Yervent Zorian of Virage Logic and Erik Jan Marinissen of IMEC. No one can any longer say that the industry is not focused on addressing 3D test.







Zorian



Marinissen




The technical program consisted of: an Opening Keynote by Bob Patti of Tezzaron); an Invited Address by Brion Keller of Cadence; invited talks by Synopsys, ARM, IMEC, Qualcomm, Avago Technologies, ST-Ericsson, and Texas Instruments and technical papers from Cascade Microtech, Virginia Tech, Fraunhofer, TU Delft, NCSU, Mentor Graphics and, TSMC. The conference had financial support from  Advantest, ARM, Intellitech, Mentor Graphics, Scanimetrics, Synopsys, SynTest, Tezzaron , and Tokyo Electron.




IEEE Computer Society 3D Test Standardization Group




Marinissen presented the early results of the IEEE Computer Societies TTSC Standardization study group on 3D Test. Most of the major players are participating






The following standardization needs have been identified:






Tezzaron

Bob Patti once again reiterated that the killer application for 3D IC will be what he calls “split die”, i.e. removing embedded memory from SoC and bonding it directly to the logic chip as shown below.






Tezzarons form of BIST is called Bi-STAR™ by Patti, who claims that it “..tests and compares 2304 bits/clock cycle; more than 100 times faster than can be achieved by any external memory tester” Reportedly Bi-STAR can test and repair:

• Bad memory cells

•Bad line drivers

•Bad sense amps

•Shorted word lines

•Shorted bitlines

•Leaky bits

•Bad secondary bus drivers

•Bad CAMS

Cadence

Sanjiv Taneja of Cadence lists the following as Design and Test Challenges

• Front-end design

– Logic synthesis with 3-D partitioning

– Logic synthesis with 3-D physical awareness

– 3-D design/timing/power constraints

– Equivalence checking across multi-chip RTL/netlist

• Physical design and analysis

– 3-D floorplanning and partitioning

– Thermal/TSV-driven placement

– Global and detailed routing with TSV

– Parasitic extraction with 3-D electrical modeling

– IR drop and thermal analysis with TSV, Silicon interposer

• Chip-package co-design

– 3-D connectivity checks and constraint management

· Test Challenges

– New defect types (defects due to thinning, TSVs)

– TSV Interconnect defects

– Limited test access with challenges similar to SiP

– Redundancy and repair of TSVs

– Key Technical Requirements

• Ultra-low pin count compression

• Reduced Pin Count Test

• Pattern Fault model

• 1149.1/1500 support

• Creation of KGD after wafer test

• A means to test the TSV interconnect between stacked die

• A means to test inside the die of the stack

Cadence points to the integration of design and test as the only way to solve these complex issues and that concurrent optimization for area, timing, power and testability is the only means to achieve required predictability.










Cascade Microtech – Probing of TSV at 40 um pitch

Ken Smith of Cascade Microtech indicates that contact probing of TSV interconnects requires much higher density, lower probing forces, and lower cost per pin than conventional probe cards can achieve.




Smith claims that there is no known physical roadblock to scaling basic card mechanics to much smaller dimensions. To reduce the probe pitch by a factor of k, the basic scaling required is to reduce all of the probe’s dimensions by k, along with maintaining constant pressure at the probe tip.




Cascade claims their high-density MEMS probe card technology make 1 gram tip forces feasible and very low pad damage possible at 40 micron array pitch.






In order to minimize pad damage, it is desirable to probe at the lowest force range that yields stable contact resistance. Contact resistance is a function of probe tip size, shape and metallurgy; probing force (pressure); substrate metallurgy; test current level; and contact cleanliness (determined by the cleanliness of the probe tip, DUT surface, test environment as well as the cleaning regimen).




Smith claims that “..the measured results to date indicate successful scaling of mechanical probing to array pitches of around 40 um. Practical probe cards are capable of 40 um pitch and tip forces below 1 gm. These lithographically fabricated probe cards enable scalability to lower cost just as IC linewidth scaling has reduced the cost of IC functions. Instead of probe costs being roughly proportional to pincount, the cost of a MEMS probe is roughly proportional to the probe area”




Smith reports that pad damage at these low forces is extremely small with scrub marks less than 100 nm deep.

We will continue our discussions on the 3D Test Workshop in the next blog including an exclusive photo of the IEEE 3D Test with a surprise model !




For all the latest on 3D IC Integration and Advanced Packaging stay linked to IFTLE…..



















IFTLE 27 Era of 3D IC Has Arrived with Samsung Commercial Announcement

December 12, 2010 12:48 PM by Garrou

Back in Nov 2008 PFTLE called on Mick Jagger and “Mr Jimmy” to explain why we “don’t always get what we want". What we wanted two years ago were commercial announcements, from someone, from anyone using 3D IC technology. [ see PFTLE 53, “You Can’t always Get what You Want”] While there were no blockbuster announcements that week in the fall of 2008 we did get assurances that the industry was steadily, if not rapidly, moving forward and that we are not wasting our time or money chasing this technology (or at least we hoped so).


Well, we often hear that “all things come to those who wait” and indeed this past week for those of us who are 3D prognosticators, our dreams have come true. Not that there was any reason to doubt after the Elpida,UMC, Powertech partnership announcements of this past summer, but I’m sure lots of 3D enthusiasts broke out the champagne this week after the announcement by Samsung. Both the Elpida and Samsung announcements contain all (3) requirements for full 3DIC; i.e thinning, stacking and TSV.


Similarly, this weeks IBM announcement following the Xilinx /TSMC/Amkor announcement a few weeks ago [ see IFTLE 23, “ Xilinx 28 nm Multidie FPGA…” ] gives added credibility to the commercial viability of high density interposers with TSV for advanced packaging solutions. With multiple announcements in each category now “under our belts” IFTLE proudly announces that the Era of 3DIC has arrived.


As was the case with image sensors [ see PFTLE 46, “.....on Mechanical Bulls, Rollercoasters and CIS with TSV” ] we can expect other memory producers to follow with announcements or eventually loose market share. Will Hynix or Micron announce next ?


Samsung Memory Stack


On Dec 7th Samsung announced that it “…has begun mass production of 8GB DDR3 memory modules based on the SODIMM form-factor used by many notebooks and mobile workstations”. The modules are based on four-gigabit, 1.5V, 40 nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking technology. A single 8GB DDR3 module using the new technology is claimed to offer a 53% power savings compared to two 4GB DDR3 modules, and a 67 percent power savings compared to 1.8V DDR2 components. Samsung announced plans to apply the higher performance and lower power features of this TSV technology to 30nm-class and finer process nodes. This is only a two chip stack, but it is the beginning.
The modules are purposed for use in high performance servers where its TSV technology is a key to lower power consumption while increasing memory capacity and improving performance. Adoption is expected starting in 2012. The modules will be available as an option in Dell's Precision M6500 mobile workstation, which will fill four slots totaling 32GB of memory. There was no indication of pricing or price comparison to non 3D components.







IBM 3D Interposer


The following day, IBM and Semtech announced that Semtech will use IBMs 3D TSV technology to develop a high-performance ADC/DSP platform for “… fiber optic telecommunications, high performance RF sampling and filtering, test equipment and instrumentation, and sub-array processing for phased array radar systems”.


Calling the technology a “… first-generation 3D multi-chip module” Semtech will utilize IBM's 300 mm 3D interposer technology to interconnect ADC functions in IBM custom logic (SOI-based Cu-45HP technology) with interleaver ICs (IBM's 8HP BiCMOS SiGe technology). The disparate technologies are connected through a single 90 nm wiring layer on a 3D interposer, which supports a bandwidth of greater than 1.3 Tbps in this design.


Ultra high density capacitance is provided by integrating deep-trench (DT) capacitors at the top surface of the interposer. The interposer connects to the next level package with copper TSV technology. The figure below shows SEM cross sections of the interposer chip and deep trench capacitors.


IBM will provide semiconductor fabrication, wafer finishing and assembly for Semtech. Integration of data converters with DSPs reportedly has been a difficult problem due to mixed IC technology requirements and lack of high power, high bandwidth interconnect. The 3D technology allows integration of the CMOS and SiGe technology at very high bandwidth and with low power to provide a high-performance module solution.


Semtech will have first ADC/DSP prototype modules available in 2011. Near-term applications include 100 Gbps coherent receiver for fiber optic telecommunications, high performance RF sampling and filtering, test equipment and instrumentation, and sub-array processing for phased array radar systems.





GSA Creates 3D Integrated Circuit (IC) Initiative




The GSA (Global Semiconductor Alliance ) has announced a new 3D IC Initiative. The GSA’s goal is to help accelerate an industry-wide transition to make 3D IC technically feasable, as well as cost-effective, for a wide range of applications and increase ROI for early adopters.


Part of the 3D IC initiative includes the formation of the 3D IC Working Group which will include participants from the major semiconductor companies, the supply chain including EDA, packaging and foundry. The GSA hopes to continue to work with other interested organizations on standards and other synergies to drive economies of scale and therefore has initiated relationships with IMEC, ITRI, SEMI , SEMATECH and Si2 to help in such efforts.


The GSA will hosts its second annual Memory Conference on March 31, 2011 in San Jose. The theme for the 2011 conference will be Memory and Logic Integration and the Benefits of 3D IC Technology.


SEMATECH /SIA /SRC Initiate 3D Enablement Program


SEMATECH, the SIA (Semiconductor Industry Association) and the SRC (Semiconductor Research Corporation) have established a “3D enablement program” to drive industry standardization efforts and technical specifications for 3D heterogeneous integration.


The new 3D program, launched by a group of existing member companies in SIA and SEMATECH, will focus primarily on developing technologies and specifications necessary for establishing standards in critical areas such as inspection, metrology, microbumping, bonding and thin wafer and die handling. To achieve this, SEMATECH will partner with SRC to enable select university research projects. The program will address these industry infrastructure gaps in phases. First efforts will focus on developing the necessary standards and technical specifications, followed by planning activities to identify the key areas for developing design tools to support 3D chip design.


The 3D Enablement program is open to international fabless, fab-lite and IDM companies, outsourced assembly and test (OSAT) suppliers, and tool vendors.


Coming up next;


…..IEEE 3D Test Workshop
.….IEEE 3DIC Conference
.….IEEE IEDM
…..RTI 3D-ASIP


For all the latest in 3DIC and advanced packaging stay linked to Insights From the Leading Edge….







IFTLE 26 Adv Pkging at the 2010 ESTC

December 3, 2010 8:10 AM by Garrou

The ESTC (Electronic System integration Technology Conference) was set up to be the European equivalent to the sister ECTC (USA) and EPTC (Asia) conferences. This years conference in Berlin attracted ~ 480 attendees who saw 160 presentations, 4 poster sessions, a 3-day industry exhibition, workshops and short courses.




Rolf Aschenbrenner (right) , President of IEEE CPMT overlooks ESTC in Berlin




ASE - Cu WB


We have previously discussed the significant inroads being made by Cu WB (wire bonding) [ see PFTLE 86 “ Advanced Packaging from Rimini ”, 07/12/2009 ]. At the ESTC ASE’s Bernd Appelt gave a update on the status of Cu WB in ASE.


Cu WB has been around for some 20 years but up till now has been limited to high power applications with wire diameters over 2 mil. Now that commodity gold prices have surpassed $1000 / oz there is significant demand to drive down the cost of gold WB. Fine diameter Cu wire refers to wire diameters below 1.2 mils, normally 0.8 mil, either Cu wire or Pd coated Cu wire (Nippon Steel).


Gold is very resistant to oxidation and corrosion. . While copper has electrical, thermal and mechanical advantages it also presents challenges due to the mechanical properties as well as its propensity for oxidation and corrosion. To overcome Cu oxidation during electronic flame off (EFO) that leads to a free air ball (FAB) of an undesired appearance, forming gas ( 95% N2, 5% H2) is widely used. Spherical ball shape is a good indicator that an ‘oxide free’ ball has been formed.


According to KNS, the cost of Pd-coated wire is currently about twice that of bare copper wire, but still offers savings over gold wire. The palladium coating greatly reduces oxidation on the surface of the wire. allowing a nitrogen gas atmosphere (no H2) during ball formation. The oxide-free surface of Pd-coated wire also results in a more robust stitch bond with higher stitch bond pull strengths and the shelf life of the Pd-coated wire is longer than bare copper wire.


Al splash, which can be quite pronounced, must be contained within the bond pad opening (BPO) as shown in the Fig. below. Residual Al thickness should be 100 nm minimum. This thickness typically survives JEDEC temp cycling of more than 1000 hrs.





The wire pull and ball shear strength at time zero are considerable higher than for corresponding Au wires although the AlCu intermetallic compounds is very thin.




The mold process and pre-mold plasmas do not require any change other than the usual optimizations of plasma. Concerns have been raised about the reliability of standard mold compounds as do to the propensity of oxidation and corrosion of Cu.


ASE reports that reliability has been demonstrated to exceed 2x standard JEDEC testing and is continuing. More than 400 million devices have been shipped by ASE from six different factories. More than 1,500 wire bonders are running with Cu wire and they expected that by the end of 2010 this number will increase to 3,000.


KNS – Thin Die Pick and Place


Common attributes to all thin die processes include: 1) relatively long pick times (typically 300 to 600 msec) to avoid cracking of the dice and 2) relatively long place times (500 msec up to 2 sec) in order to guarantee good die attach quality. Peeling the die from the wafer mounting tape typically requires a large vacuum suction force which can be achieved by a large number of large diameter vacuum holes. On the place tool, however, the large vacuum holes need to be avoided in order to minimize the die deformation during the place process, since this can lead to undesired air inclusions (voids) between the die and the substrate or the underlying device. KNS describes their parallel pick and place architecture (shown below) which they claim both units per hour and die attach quality. With the parallel pick and place architecture the pick process of the subsequent die can already be initiated during the place process of the first die.








ST Micro/ ST-Ericsson / Leti – WB vs 3D IC




ST Micro, ST-Ericsson and CEA Leti showed results of their study comparing a wireless video product built and compared in WB vs TSV constructions.


Chips were fabricated using a 65nm node CMOS process including seven Cu metal layers with low-k. TSV were 60μm diameters on 120μm pitch in 120μm thick wafers. Cu pillars used for die to substrate connection were 70μm diameter on 130μm pitch and 80μm height. The BGA package (4x4mm) included 65 balls on 0.4mm pitch.




In their test case, no significant performance differences were seen between both versions of the product. ESD, considered a crucial topic for 3D integration was examined. They noticed no major difference between the two versions of the products, concluding the TSV version of the product did not exhibit a more critical ESD behavior. They conclude “there’s no important show-stopper with the technological bricks that are currently available for TSV integration today”




On Semi – Low Profile WLP


To meet requirements for thin smart phone products, ON Semiconductor has developed “LPCSP” a low profile CSP (WLP) with a 0.275 mm thickness.





While it is well known that increased solder ball height increased reliability, the goal of 0.275 mm thickness could only be achieved by reducing the ball height and/or the silicon wafer thickness. A silicon thickness of 200 um was chosen due to automated handling equipment limitations. The LP-CSP technology does not require special assembly handling, additional assembly steps or underfill. It is clear from the data that both silicon thickness and bump height reduction were necessary to ensure board level reliability performance of the LP-CSP is comparable to WLCSP.




IMEC / Amkor – Reliabilty of Cu-Sn IMC Microbumps in 3D Stacking


IMEC and Amkor have studied thermal cycling and electromigration, on fully packaged Si-to-Si stacks bonded with Cu-Sn intermetallic (IMC) micro-bumps.


While the presence of small voids at the interface between Cu and Cu3Sn becomes more pronounced with continued ageing, during thermal cycling, these voids do not affect the daisy chain resistance during temp cycling between -40 and +125 C. The Cu-Sn IMC bumps survive thermal cycling for more than 3900 cycles.


Resistance to electromigration appears strongly dependent on Sn thickness showing an improved performance for thinner (3.5 µm) vs thicker (8 µm) Sn. For 8 μm Sn bumps, almost all available Cu is fully consumed (5μm on each side of the joint) and the Cu3Sn phase reaches the Cu damascene layers. Voiding inside these thin layers is reportedly detrimental to the interconnection stability. A more conservative ratio of Cu and Sn is therefore suggested.

While IMC bumps outperform standard solder flip chip bumps, the authors recommend that an overall reduction of the void formation may be advisable for further reliability improvement.

They conclude that appropriate packaging of these Cu-Sn IMC bonded Si-stacks results in overall excellent thermo-mechanical and thermal-electrical behavior for various reliability test conditions which makes them highly suitable for connecting fine pitch advanced substrates.

Amkor – Wafer Level Fan Out

When it comes to fan out WLP Amkor has appeared behind Infineon partners STATSChipPAC and ASE. Amkor presented wafer level fan out technology developments using Ajinomoto build-up film (ABF), laser ablation via generation processes and buried pattern PCBs, which they claim results in low cost and high electrical performance.

In the first process ABF is laminated to the reconstructed compression molded wafer, micro-vias are formed by laser drilling and Cu RDL interconnect is plated and pattern defined.




A second process based on a buried-pattern PCB substrate was also described for fabrication of FO WLP. By using buried-pattern PCB, similar to what is used for high density BGAs, laser ablation of the vias is not necessary. The buried-pattern substrate is delivered from PCB manufacturer with open (non filled) through vias which are seeded and plated from the backside after front side chip attach. After polishing, RDL and ball placement the devices are singulated.



Fraunhoffer IZM – Thin Stackable Embedded Chip Packages

In two separate presentations researchers from Fraunhoffer IZM and coauthors detailed now methods to construct thin stackable packages.

Under the framework of the EU-funded project “HIDING DIES” program industry and research organizations worked with Fraunhofer IZM to develop embedding technology based on embedding thin chips into build-up PCB materials. Electrical contacts to the chips are realized by laser-drilled and metalized microvias. A follow up EU-funded project “HERMES” has the broader scope of furthering the embedding technology and bringing embedding technology into production with the goal of embedding components in 18 x 24 inch PCBs.

Dies can be either placed face-down on the substrates or face-up. The Fraunhofer IZM technology focuses on the face up approach in combination with the formation of laser micro vias. The process flow is shown below using resin coated copper (RCC) to embed the die:







A QFN package results when the chip is attached to a metal substrate as shown below. Both top and bottom contacts are directly accessible for better heat dissipation which is of importance for devices like power chips.




Such structures can also be stacked into 3D PoP configurations.



Infineon – eWLB


Infineon presented the latest developments in connection strategies for 3D-eWLB and the challenges of the technology this development.

Multichip- eWLB – a minimum distance between two dies is set, depending on amongst other things the size of the filler particles. Typically the minimal fillable gap is 2.5 times the maximum filler size, but this is also depending on the thickness of the silicon die(s). They report excellent mold compound filling behavior of 250 μm die to die gap. After the pick and place process step, no special multi-die specific process step are reportedly needed. The wafer is molded with standard mold compound and the same dielectrics and redistribution lines are applied as for the single die eWLB. Die shift and wafer warpage after molding was found to be equal to single die eWLB. Reliability testing including Temp cycling and BLR drop testing showed no difference between eWLB and multichip eWLB.

Stacked eWLB (or ePoP) - the technical advantages of eWLB PoP stacking are reported to be :
- Low profile and small lateral dimensions
- No interposer requirement (reduced number of interconnects, reduced cost)
- Use of top packages with standardized ball array

Connection in z-direction for a “ePoP” package can reportedly be realized in two ways.
- drill via holes by laser
- via bars, produced in PCB technology, can be molded into the reconstituted wafer

The process flow for the latter is shown below. The chips and the PCB based bars are placed on the mold carrier and the reconstituted wafer is generated via compression molding. After reconstitution the artificial wafer is ground down to make the via bar accessible for the connection with a redistribution layer. It consists of a dielectric on bottom side, redistribution layer and solder stop on top and bottom side.

Hope to see many of you at next weeks RTI 3D-ASIP conference in Burlingame CA (link)



For all the latest on 3D IC Integration and Advanced Packaging stay linked to Insights From the Leading Edge, IFTLE…………………














IFTLE 25 IMAPS Part 2 Advanced Packaging

November 27, 2010 8:03 AM by Garrou

IBM Going Fab Lite ??

Peter Clarke of EE Times is reporting that “ … IBM appears set to gradually back away from semiconductor manufacturing and to rely for its leading-edge silicon on Samsung and GlobalFoundries as foundry suppliers ( link ). If you are a reader of IFTLE you already knew that [ see IFTLE 8 " 3D Infrastructure Announcements and Rumors ”, July 2010]

“… IBM is gradually allowing itself to exit from leading-edge manufacturing at high volume. IBM appears to have joined the broad class of semiconductor companies that will never build a major wafer fab again” reports Clarke. Interestingly the last time that IBM was close to the global top 10 was in 204 when they ranked 11th.

Several Govt. types were shocked when I shared this rumor a few months ago. Clearly they shouldn’t have been. It appears that such business decisions will take what remains of IBM manufacturing prowess the way of Bell Labs, DEC and many of the other early giants in our USA microelectronics industry..



Advanced Packaging at IMAPS National



IBM Injection Molded Solder


IMS is a variation of C4NP for solder deposition on fine-pitch laminates.




The presentation on this technology is examined in detail in the ElectroIQ advanced packaging section by the presenter Jae-Woong Nah [link]: 


RTI Int

Alan Huffman of RTI Int presented an overview of the evolution, status and possible future for bumping /WLP which I co-authored. RTI, as you know, purchased the Microelectronics Center of NC (MCNC) ~ 4 years ago. MCNC spun off Unitive which is now owned by Amkor but “back in the day” bumping pioneers such as Iwona Turlik, Dan Mis, Glenn Rinne, Paul MaGill, Phil Deane, CJ Berry, Ted Tessier, Boyd Rogers and many others developed a plated bump process that is still used globally today. In fact the joint industry standard on “implementation of flip chip and chip scale technology” put out in 1996 by EIA/IPC/JEDEC/SEMATECH/MCNC was put together at a meeting on the MCNC campus.


Historically flip chip (or C4 as IBM called it) had been around since the 1960s but things took off commercially in 1992 after Tsukada of IBM Japan announced that they had discovered that the use of underfill allowed reliable joints directly to PCBs (i.e chip-on-board). After the commercial use of flip chip in the Motorola StarTac cell phone in 1996 the commercial use of flip chip in consumer products exploded.


It is clear today that flip chip and WLP are evolving into copper pillar bump (lower electrical resistance and inductance; lower thermal resistance; better resistance to electromigration; reduced pitch) and WL fan-out packaging (allows more IO at same pitch). A complete description of Huffmans presentation is given in a podcast interview with SST Editor Debra Vogler which can be accessed here [ link ].

Micron
Micron's presentation on the next generation of PoP (package on package) indicated that there would be a required reduction in Z height of the top memory package. This in turn will require reducing die thickness and reducing the mold cap thickness.


While transfer molding is the standard mold method used in the semiconductor industry, this method has limitations when it comes to very low mold cap clearance. Issues include mold voids, bond wire sweep, and filler segregation.


Compression molding has been introduced in fan-out WLP for full wafer molding. Micron now reports that compression molding of PoP top memory packages is the most suitable molding method for structures with reduced mold cap thickness.


A key parameter for PoP packages is the warpage during reflow. Shadow Moiré was used for measuring package warpage. The study found that compression molding and transfer molding yielded equivalent package warpage when using the granular forms of mold compounds. For top PoP packages that tend to have thin mold caps, Micron reports that it is necessary to choose a mold compound with lower coefficient of thermal expansion CTE1 (below Tg) and CTE2 (above Tg) and lower cure shrinkage.


Finite element simulations indicated that the coplanarity, as well as warpage of small size packages (12mm x 12mm and below), could be controlled to under 100 μm.


NEPES


We have recently reported on NEPES licensing of the Freeescale RCP (redistributed chip package) technology for fan out packaging [ see IFTLE 2, “ Advanced Packaging at the 2010 Las Vegas ECTC ”, June 2010].


At the IMAPS National meeting NEPES took another major step in advanced packaging when they revealed the details of their silicon module (SiP) program silicon module with Cu filled TSV and IPD (integrated passive device) LPF (Low band pass filter) integrated at the surface of silicon interposer as shown below.




The 7 mm x 7 mm Si interposer is 200 um thick. The entire package is limited to < .8 mm thickness. The spiral inductor is formed in the backside RDL layers from 8 um ED copper in low K polymer. MIM capacitors are fabricate by Al/SiO2 front end TF (thin film) processes and Cu/polymer back end processes.

The LPF shown below is fabricated from two inductors of 2.508nH, one inductor of 5.24nH and two capacitors of 1.641pF fabricated by front-end Al/SiO2.





For all the latest in 3D IC integration and advanced packaging stay linked to IFTLE………….




IFTLE 24 IMAPS National Summary Part 1 - 3D Highlights

November 20, 2010 2:06 PM by Garrou

The IMAPS USA annual or “National”, as it is known, was held in Raleigh a few weeks ago. Rajen Chanchani of Sandia National Labs took over the helm as IMAPS President during this meeting with long time industry stalwart Voya Markovich next in line. Rajen’s name should be familiar to all packaging practitioners since he was part of the team that developed the Sandia mini BGA back in 1997 [see “Mini Ball Grid Aray Assembly on MCM-L Boards”, ECTC 1997] which WLP historians like Peter Elenius and yours truly credit as the first WLP structure. Voya, all of you know for his decades long development of high density PWB solutions such as “film redistribution layer technology” at IBM and subsequently Endicott Interconnect . The photo below shows the assemblage of past IMAPS presidents that were at the Raleigh meeting.




Meeting General Chair was Dave Seeger who at the time he signed up was on loan to SRC here in the Research Triangle, but since has moved back to IBM in NY. Technical Chair was Sara Paisner from Lord which is headquartered here in the RTP area.




This years meeting had a significant 3D focus with several professional development courses and 5 sessions which included a panel session on “Roadmaps, Technical and Business Progress” We’ll first take a look at 3D and in the next blog look at other topics in in advanced packaging.


3D IC Panel session



The 3D panel session was headed up by RPI Professor James Lu, panelists are shown below:




IMAPS 3D Panel: Phil Garrou (Microelecttronic Consultants of NC); Nick Sillon ( Group Manager, CEA Leti); Klaus Hummler ( Sr Principal Engineer, Sematech); Urmi Ray ( Sr staff engineer, Qualcomm); James Lu (Professor RPI); Rozalia Beica (Program Director, EMC3D); Dorota Temple ( Program Director, RTI)



When asked about the 3D commercial timeline I commented that roadmaps of many companies (TSMC, UMC, Elpida, ASE etc.) now appeared in sinc and all point towards commercialization in the 2011-2012 timeframe. Ray commented that Qualcomm, a very public supporter of 3D IC technology , sees “two years out (2012)” as “about right”. Hummler was a little more hesitant about timing indicating that “…Nokia is pointing towards product introduction in 2013 but we believe this will be a stretch”. Beica indicated that 15 3D lines were going in place across the world (I assume this included commercial, university and institute lines)


When asked about standards, Ray, herself involved in several standards initiatives, pleaded for more work on standards “now”. Hummler commented that for fables companies standards are a “matter of survival” .


When questioned on the role of consortia and institutes, Sillon responded that “…the role of consortia is to show demonstrators of what can be done with 3D” .


Temple reminded the audience that 3D allows “.. separating digital from analog layers which results in lower power product developments” She also pointed out that we may need what she called “Second generation OSATS” which would be skilled in “..processing not usually done by the OSATS today”.


Sematech


As we have noted in the past Sematech’s role in the 3D IC infrastructure is to">drive convergence of the materials/equipment solutions by:
– creating roadmaps and standards
– working with others including Member Companies to drive convergence
– industry consensus building through workshops and forums


Klaus Hummler, who has recently moved to the Sematech Interconnect program from siXis, discussed their technical focus area namely “Via-middle” ( TSV’s formed after FEOL and before BEOL) with the following attributes:


• TSV before 3D stacking
• Wafer thinning before 3D stacking
• Back-to-face bonding
• Die to wafer bonding
• TSV diameter 5 μm
• TSV pitch 10-50um
• 20-50 μm TSV depth


Long time readers will note that this is exactly where IFTLE (and PFTLE) has been pointing you for the past 3 years.


EMC-3D / Applied


The name Rozalia Beica has become synonymous with 3D IC in the past few years. Rozalia has been one of the “faces” of the EMC3D consortium [ see PFTLE 47, “ 3D IC Questions and Answers from the EMC-3D Consortium ” After the acquisition of Semitool by Applied Rozalia rejoined the Semitool business unit of Applied Materials working in their 3D program. Processes supported by EMC3D are shown below:






Applied has put together a lineup of tools to address TSV fabrication as shown below (sorry for the small print). Beica reports that Applied, at their Mayden Development center 3D line have  run more than 50 integrated demos.








Beica reported that their newer via fill processes show a 50% reduction in overburden and significantly purer copper which results in significantly less Cu extrusion (Cu pumping) and micro voiding.

Paul Enquist, CTO of Ziptronix reports that their direct bond oxide technology catching on with fabricators of backside illuminated CMOS image sensors. Enquist also shared the first released cross sections of a 10 µm pitch, 463,000 connection daisy chain built with the Ziptronix DBI process with Cu filled TSV fully protected by barrier layers (below). Enquist reported a 99.999% yield on such structures.





John Lannon, Sr engineer at RTI Int described the RTI bonding process developments. He warned the audience of electrical failures during reliability testing of 3D test vehicles bonded with Cu/Sn/Cu intermetallics, “…the yield goes to zero after 96 hours standard autoclave testing” Lannon added “ …standard epoxy underfills do not seem to solve the problem, but we have found a silicon underfill that allows device survival through the autoclave testing. More work is needed to completely understand this issue and all potential solutions“ An interesting dialog occurred during the question and answer period of Lannons presentation. An unknown questioner from the back of the room stated that Cu/Sn/Cu bonding used by so many of today’s 3D IC practitioners was nothing more than copper pillar bonding and that (paraphrasing) “…copper pillar bonding is patented by APS and anyone practicing this technology must be licensed by APS”. APS is of course Avanpack in Singapore and indeed I am aware that Amkor, Unisem and Flip Chip Inc have taken out such licenses. I do not support or reject the questioners statement without further study (yes – I do serve as an expert witness !) but I certainly do bring it to your attention.


Rhett Davis, Professor of EE at NC State showed much od the work that he and fellow Professor Paul Franzon have been doing in the 3D area. 3D specific designs were shown that achieved 65% power reduction and an 800% increase in memory bandwidth.


Jeremy McCutcheon of Brewer Science reviewed their Zonebond process (link) showing the audience significant details on the carrier removal step once the wafer is laminated to a film frame. McCutcheon warns that “… solvent strip on film frame an issue since some solvents attack the glue on the film frame. This step must be done properly”


Between now and the end of the year IFTLE will be looking at:


- Napa KGD conference
- IEEE ESTC Conf
- IEEE 3D Test workshop
- IEDM

- RTI 3D ASIP Conf
...as well as any and all announcements and rumors that you need to be aware of.



RTI ASIP

The RTI ASIP Conference (3-D Architectures for Semiconductor Integration and Packaging) will be held in Burlingame CA on Dec 8-10. 3-D ASIP is focused on technology advancements, business issues and infrastructure development. Among the many invited speakers are Erik Volkernik CTO of Verigy, Subramanian Iyer of IBM, Doug Yu of TSMC, Ho-Ming Tong of ASE, Bob Patti of Tezzaron, Arif Rahman of Xilinx, Marc Scannell of Leti, Bob Lanzone of Amkor and many, many other industry experts. Hope to see you there.



For all the latest in 3D IC and advanced packaging stay linked to IFTLE………………………….






IFTLE 23 Xilinx 28 nm Multidie FPGA, Copper Pillar Advances at Amkor and Intel Looking at Foundry Options

November 7, 2010 4:31 PM by Garrou

Took a little time off to have Halloween with grandaughters Hannah and Madeline in Houston. If you’re a kid in America what a great holiday Halloween is. Basically, strangers give you candy for dressing up and pretending to be someone or something your not. Hummm…come to think of it, this is a bit like politics where politicians pretend to be something their usually not (honorable, honest, concerned ) when really all their after is the candy. When it comes to trick-or-treat we are usually the ones who are tricked. Well that’s a discussion for another day. Hannah (6) and Madeline (2) certainly had a great time as you can see below.






Xilinx 28 nm FPGA will use Si Interposer



The true 3D aficionado has been waiting for the first true commercial product announcement. We already have face to face stacking without TSV (chip-on-chip in the Sony Playstation and many other products) and TSV being used for 1 layer image sensors (nearly all of todays CMOS image sensor manufacturers) but when will we see a true 3D design which will contain (a) TSV, (b) stacking and (c) thinning ?


We were teased this past week with headlines such as “Xilinx Stacked Silicon Interconnect Extends FPGA Technology to Deliver 'More than Moore' Density, Bandwidth and Power Efficiency”. I must acknowledge that it does not directly say anything about 3D, but there certainly was a lot of buzz in the industry since the packages make use of TSV interposers.


We have seen a lot of structures recently that use the silicon interposer to mate die to the top and bottom of the interposer (i.e the Renesas SMAFTI) . Last week Xilinx announced a single layer, multi chip silicon interposer for its 28nm 7 series FPGAs. These FPGAs reportedly extend the range of applications programmable logic can address by offering up to 2 million logic cells for high levels of computational performance and high bandwidth.


The 28nm Virtex-7 LX2000Tmulti die FPGA will provide more than 3.5X the logic for capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers.


Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources. By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid any thermal and/or design issues that would be introduced had a pure 3D IC vertical die-stacking approach been taken. This will reduce power, and improve performance compared to a multi-FPGA approach


Xilinx reports that they have been working with TSMC and their assembly house Amkor. The device is made possible by Amkors micro-bump assembly, FPGA architectural innovations from Xilinx, and advanced technology from TSMC. The new products deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application.


By using TSV silicon interposer to implement their stacked silicon interconnect approach, Xilinx reported that they “ reduced the risk involved with thermal and design issues of full 3D IC stacking” This probably means that full 3D just is not ready yet and we will be seeing more ”Xilinx like” designs in the near future before we see full 3D in a few years from now.





According to Xilinx, Initial devices will be available in H2 2011.




For more technical information including white papers, visit the Xilinx web page at: http://www.xilinx.com/stackedsilicon.


Amkor /TI Copper Pillar Technology


The week before Semicon West Amkor and TI announced that they had qualified and begun production of the industry's first fine pitch copper pillar flip chip packages – shrinking bump pitch up to 300 percent compared to current solder bump flip chip technology [ link ]


Very little follow up was available because of the exclusivity TI was given as part of the joint development program. The publically available data left me once again asking “Where’s the Beef” [ see IFTLE 3 "… on finding the beef and finally addressing 3D IC "]


I was personally told that full technical details are being withheld till the next ECTC conference [ June 2011].


Last week Amkor did release come details on their technology. For all the available information on this technology see the amkor website here ( AMKOR ) . Design rules are shown below.






The Weibul plot shown below shows an improvement in life for Copper Cu pillar over SnAg bump for the same current / temperature condition and similar bump / UBM geometry. No failure was observed in Cu Pillar Bump even after 8000 hours of testing at the same condition.



Fellow blogger Dick James has done some reverse engineering which can be found here (link).[added 11/09/2010]




Intel Becoming a Foundry ??


Intel has agreed to manufacture a specialized microprocessor design for Achronix Semiconductor at its most advanced factory [link]. While the production use less than 1% of Intels production capacity, it certainly is a departure from their normal business model and may point to their experimenting in the foundry business to keep such options open for the future. While Intel is brushing this off as non important, I would kep an eye out for similar developments.

For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edge….
















IFTLE 22 Sources for Fanout WLP Continue to expand

October 29, 2010 9:24 AM by Garrou

FO-WLP (Fan-Out Wafer Level Package) is the general term for a type of package that employs wafer-level redistribution technology and supports formation of redistribution layers outside the chip area. FO-WLP has been discussed numerous times [ see Solid State Technology, “ Highlights from the ECTC ”, 06/15/2010; PFTLE 72, " The Samsung Roadmap That Isn't ", 04/16/2009] .The first 200 mm FO-WLP wafers were mass produced at Infineon, STATS ChipPAC and ASE in 2009. It is quite apparent from its successful introductions that it is becoming the next BGA in terms of package popularity.



Current FO-WLP practitioners include licensees of the Infineon e-WLB [embedded wafer level BGA] including ST Micro, ASE, STATSChipPAC and Nanium (Qimonda Portugal) and Nepes which has licensed the Freescale RCP [redistributed chip package] technology which is similar.. Amkor and others are known to have similar products in development.


The 2010 marketplace for FO-WLP, as determined by Yole Development, is shown below.






At the September IEEE ESTC meeting in Munich, Renesas announced their entry into the FO-WLP club. Recall that the new Renesas is a merge of Renesas and NEC which began combined operations in April 2010 [link].




Their technology will first be used in microcontroller (MCU) products, which require small chip size and high interconnect density. Their listed specs include: interconnect density (L/S = 15/10 μm, interlayer via pitch = 50 μm); chip size (5 mm × 5 mm or less) and thickness (0.3 mm) package.


The process flow involves following steps: (1) Photo PI is deposited on a Si support wafer and the patterned; (2) Cu RDL is deposited and patterned using a semiadditive process; ( design rules for Cu wiring were 15 μm in width, 10 μm in space, and 5 μm in thickness); (3) Cu pillar bumps (CPB) with Sn-Ag solder caps were formed at relevant positions on the top Cu wirings; (4) IC chips were separately prepared with electroless Ni/Pd/Au plating on I/O pads; (5) chips attached by die-to-wafer bonding; (6) MUF (molded underfill) of the chip-bonded RDLs on the support wafer; (7) The Si support wafer was removed from the chip-bonded RDLs to form a chip-embedded resin wafer with RDLs; (8) The wafer was diced and separated into an individual packages (Before dicing, additional metallization for external terminals such as Au plating, solder ball mounting, or solder paste printing occurs).






Below we see a 1.6-mm square 8-bit microcontroller chips with the 75-μm-pitch I/O pads were assembled in a 2.0 mm x 2.0 mm FO-WLP with 2-metal fan-out RDLs. A cross-section and images of the prototype are shown in Fig. This package is a 80% reduction vs previous pkg size.






Multiple chips can be encapsulated in the same package (SiWLP™ [system in WLP]) such as the MCU and analog Rf chip shown below.



Such packages reportedly pass 1000 cycles of -40 to + 125 temp cycling. Dr. Kurita indicated that such MCU packages would be in volume production by 2012.




Next Week: Xilinx rumors prove correct, info from the IMAPS National in Raleigh.




..............HAPPY HALOWEEN TO EVERYONE ...............











For all the latest in 3D IC integration and advanced packaging stay linked to Insights from the Leading Edge….

IFTLE 21 Sabishii VLSI Japan

October 23, 2010 1:19 PM by Garrou

In late Aug 2010 the VLSI Packaging Workshop of Japan, held every other year since 1992, became The International Symposium on Components, Packaging, and Manufacturing Technology (IEEE CPMT Symp Japan) with a Conference at the University of Tokyo. Hirofumi Nakajima of Renesas was the Chairman.

Remembering VLSI Japan


VLSI Japan was an outstanding technical conference which promoted the sharing of information and ideas through the 1990’s and 2000’s. My own memories bring me back to the 2000 VLSI meeting that George Harman, Len Schaper, Jan Vardaman and I attended from the US.





After far too much Sapporo black label at a conference karaoke party, I recall Len and I led the group in singing “Hey Jude” (everyone in the world knows the words to this Beatles oldie).



As we say Sabishii (we will miss you) to VLSI Japan we say youkoso (welcome) to the new CPMT Japan symposium. From my own ancestry I offer the toast “cent’ anni” (may you live 100 years) to the new conference and its participants !


There were several interesting and informative 3D related papers presented at the IEEE CPMT Japan Symp this year that are worth reviewing.


Toray


3D stacks are usually joined by metallic bonding using techniques such as solder or Pb free solder bumps, Cu/Sn eutectic or Cu/Cu thermo compression bonding. Non conductive underfill can be used to fill in the space in and around the interconnections to mechanically support the interconnect. It is difficult to flow traditional underfill materials into such narrow gaps and to control material flowing out from the chip edges.


Pre applied non conductive filler (NCF) doesn’t need to flow into the small gaps or flow out over the chip edges. Lamination on structured surfaces demands a fluid nature for the NCF while a rigid material is required for dicing. This combination of properties can be obtained from materials that have temperature dependant viscosity. Such NCFs can flow into the narrow spaces between bumps and be cut with a standard dicing saw.


Pre applied NCF must be transparent, to allow viewing of alignment marks, and must not remain between the bump and the pad during bonding. Toray developed a transparent, low CTE underfill by using nm sized filler particles as shown in the figure below.





To get transparency from a less than 20 µm film requires filler particles less than 50 nm . Toray has achieved optical transparency, a CTE of 37 ppm/C and a 1% wt loss temp of about 350 C.




To insure that the bump / pad area is clean during bonding, the chip with NCF should be heated up to the temp where the NCF changes to a flowable liquid and then pressed into contact with the pad on the other chip in the bonder.


As an alternative solution Toray has also developed a negative tone photo NCF to insure the contact areas are free of underfill material during joining. The material flows at ~ 200 C and has a 1% wt loss temp of 300 C.


Hitachi Chemical


When filling TSV with Cu, the overburden is usually removed using CMP. The Cu thickness and topography requires a optimized Cu CMP process for removing the thick Cu layers. Hitachi studied friction force requirements and chemical additives for various slurries in order to develop a high speed removal process specifically for 3D processing. The table below shows both the target values and the ultimate product (HS-C935) performance.





Uniformity of their high speed copper overburden process is shown below.



ASET




We have discussed Japan’s ASET consortium several times in the past [ see PFTLE 104, “3D From the Land of the Rising Sun”] For the Dream Chip program Renesas and Rohm are studying thinning and pick-and-place technology for die to wafer constructions. Their specification is to achieve 10 +/- 1 µm wafer thickness stability after thinning and dicing 300 mm wafer devices.


Thinning to 10 µm requires a hard support (carrier) and an adhesive that would both be uniform and is thermally stable enough to resist degredation during grinding and backside processing.





To achieve the 10 +/- 1 µm 300 mm wafer thickness,variation must be controlled in the Si wafer, the adhesive and the carrier as shown below.

Epoxy adhesive with a reported thermal stabilty of 200 – 230 C was examined. After thining to 10 µm no edge chipping or cracking was observed, but swelling of the adhesive and resultant cracking of the thin Si is seen when the adhesive is baked for an hour at 230 C so in reality the material for this application is really only stable to 200 C.


Pick and place of these thinned chips is also a significant technical issue. They evaluated the slide-and-peel method shown below.




When the chip overhang is small the adjoining chip is damaged during the pick operation. When the overhang is to large the lower vacuum attach area becomes too large and he chip cannot be picked up. Conditions were found where the chips could be picked up by the vacuum collet.




Although it will require significant engineering, it appears that there are no insurmountable challenges when it comes to thinning and pick up. It will be very interesting to see the details on the stacking step !




MEPTEC Roadmaps Meeting




MEPTEC will be having a “ Semiconductor Packaging Roadmaps: Applications Driving Requirements” symposium on November 10 at the Biltmore Hotel in Santa Clara,CA. You can find out more about this meeting at their web page.




It will include:




Session 1: Semiconductor Industry Roadmaps: Carving out the Decade Ahead Session Chair: Rich Rice, ASE (US)




Session 2: Panel Discussion -- SATS Technology Development: Merging Internal and Customer Roadmaps Panel Moderator: Joel Camarda, National Semiconductor




Session 3: System-Level Implications on IC Package Design Session Chair:Gary Catlin, Plexus




Session 4: Packaging Roadmaps for Emerging Applications Session Chair: Jeff Demmin, Tessera




For all the latest information on 3D IC and advanced packaging technology stay linked to Insights From the Leading Edge……..




IFTLE 20 ASE Examines Materials and Process Changes for Advanced WLP

October 18, 2010 6:04 PM by Garrou

Wafer Level Packaging (WLP) is one of the fastest growing segments of the chip packaging area. WLP began over a decade ago with very small packages having very few I/O. There is currently significant demand for much larger die (greater than 7 mm) with many more I/O (greater than 150). In order to meet these requirements and continue to pass customer required board level reliability (BLR) tests (drop test and temperature cycling test) assembly houses have had to introduce material, process and structural changes to their WLP structures. For instance,



Initial WLP products manufactured under the FCT UltraCSP license (i.e Amkor, ASE, SPIL, STATSChipPAC, National, etc. )used BCB dielectric, Ti/Al/Ti RDL and Al/NiV/Cu UBM. Larger chips and more difficult reliability requirements have seen a shift to PI and PBO type dielectrics which have higher elongation and are considered “tougher”, a shift to Cu RDL and a shift away from sputtered Al/NiV/Cu UBM.


At the recent IEEE ESTC (Electronic System-integration Technology Conference) in Munich, John Hunt of ASE detailed dielectric, RDL and UBM change options for their WLP technology.





Experiments were run on a 6.36 x 6.36 mm test vehicle having a 15 x 15 array of SAC 405 solder balls on 0.4 mm pitch. The test matrix they examined is shown in Table 1. Cycles to first fail and Weibul 63.2% fail data are shown in Table 2 for the Thermal Cycling and Drop tests.













Hunt concludes that in both the temp cycling and drop test results, cell 8 shows the highest first fail and Weibul 63.2% cycle to failure data. Cell 5 would rank 2nd. Overall both cells have 7.5 um of dielectric in both the first and second RDL layers . Cell 5 uses PI and performs slightly better in the temp cycle tests and cell 8 which uses PBO performs better in the drop test.


All cells with 5 um dielectric performed poorly. Al/NiV/Cu sputtered UBM performed poorly. PBO 2 (lower cure temp – 250 C) performed better in TCT than in drop test. Higher elongation, lower modulus PBO 1 gives better drop test results.

For all the latest information on 3D IC and advanced packaging stay linked to Insights from the leading edge, IFTLE......




IFTLE 19 Semicon Taiwan 3D Forum Part 2

October 8, 2010 12:00 PM by Garrou

Continuing our look at the Semicon Taiwan 3D Technology Forum held a few weeks ago in Taipei.

Siliconware
In the past, SPIL has been rather silent about their plans for 3D IC. During his presentation at the 3D Forum, Carl Chen, VP of R and D, remarked that TSV solutions will be used short term for form factor driven reasons , mid term by performance and long term for cost considerations. This sequence is dramatically similar to the acceptance of wafer level packages (WLP) in the last decade.
SPILs roadmap shows single chip logic on interposer use in late 2010, memory stacking and logic and memory on interposer in 2011 and heterogeneous stacking post 2012. Chen commented that their 3D technology will “turn on in the very near future, depending on some technological breakthroughs and cost level”
Siliconware is calling their 2.5D interposer “TSI” for through silicon interposer. They offer the following chip-to-chip (interposer) and chip-to-wafer (interposer) sequences.
























The current status of their copper pillar joining technology is shown in the figure below.




Nokia


Nokia has been using MEMS microphones and camera modules both fabricated with TSV since 2006 and 2007 respectively.
Kauppi Kujala, Sr Tecnology Mgr at Nokia reports that memory stacking with TSV can offer miniaturization opportunities, performance improvements and power reduction.





Nokia currently sees wide I/O memory mating with logic devices as one of the main drivers for 3D IC adoption. Kujala proposes a single package with up to 4 DRAM for smart phone applications.



- 4-channel SDRAM x128 200MHz type interface, 12.8GByte/s

- Maximum memory die amount is 4 (1, 2 or 4)

- Wide IO interface grid / channel pitch of 50um

- TSV diameter of ca. 10um

- ca. 1200 uBump connection between chips




Kujala sees Interposers (2.5D) being driven by die /substrate pitch miss match and low  K mechanical fragility. Kujala, however warns that cost will be a major item in the adoption of interposers for 3D.
Nokia sees the need for standardization in areas like chip interfaces. Nokia is very supportive of JEDEC wide I/O standardization which reportedly will be ready in late 2011.

Yole Developpment

JC Eloy, CEO of Yole released their newest roadmap showing timing including initial qualification and first product on the market.






Qualcomm

Fabless Qualcomm has been a strong proponent for 3D IC over the past few. At Semicon Taiwan 2010 Nick Yu, VP of Engineering indicated that Qualcomm would like to see 3D HVM with 3D IC by 2013.


Qualcom is also a strong proponent of standardization in order to accelerate adoption of the technology. Qualcomm is suggesting specific standards in the following areas and suggested which standards bodies (JEDEC, Sematech, Semi, IEEE, Si2, ANSI) should be involved.


Design
- layout compatibility - data base compatibility
- modeling compatibility
Materials
- materials compatibility
QA
- incoming spec
Process Flow
- handling spec
Test


Qualcomm is looking for active industry professionals to contribute to these standards development programs and suggests the following venues:


3D design will be a focus area at the following 2010 events:
- Sematech 3D Stress Workshop : 19 Oct 2010, Dresden, Germany
- IEEE 3D-TEST Workshop: Nov 4, 2010, Austin, USA
- IEEE International 3D SIC Conference: 16 Nov, 2010, Munich, Germany
3D manufacturing will be a focus at the following 2010 events:
- IEEE International 3D SIC Conference: 16 Nov, 2010, Munich, Germany
- 7th RTI 3D ASIP Conf: 8 Dec, 2010, San Francisco, USA


For all the latest on 3D integration and advanced packaging stay linked to IFTLE……..








IFTLE 18 The 3D IC Forum at 2010 Semicon Taiwan

October 2, 2010 9:00 AM by Garrou

Look to Taiwan
Those that have been long time readers of IFTLE and its predecessor PFTLE know that I sometimes look at 3D IC through the eyes of someone that was part of the bumping/WLP technology explosion that occurred in the late 1990s/early 2000s. Further, if you know this history you know that while I give most of the credit for the development of most if not all of that early low cost bump/WLP technology to start ups FCT and Unitive in the USA, it was the Taiwanese who saw the power of this technology, licensed it from the aforementioned startups and put the capacity in place to make this the key technology that it is today. While fan-in WLP has evolved into fan-out WLP and copper pillar technology it has in some sense has become synonymous with “Advanced Packaging”.
Furthermore, while any commercial 3D TSV announcement is a good announcement, it is has also been clear that from the IFTLE perspective we are keeping an eye on a few key players like TSMC and Samsung because when all is said and done (a) this will be a TSV middle play and must be driven by foundries like TSMC, Global Foundries and UMC and (B) early applications will be driven by wide band memory access for memory on logic applications. So, when many of today’s 3D IC technology leaders assemble in Taiwan, it makes sense to pay attention to what they are saying. If 3D IC is to become the powerhouse technology that many of us are predicting it will, it is clear that Taiwan Inc will have to buy in and be at the forefront of leading this technology into commercialization [see PFTE 105 “Taiwanese Focus on 3D IC”, 11/06/2009 ]
2010 Semicon Taiwan 3D Technology Forum

The Semicon Taiwan 3D Technology Forum was chaired by Ho-Ming Tong, General Manager and CTO for ASE. Speakers included representatives from Yole, Nokia, Qualcomm, UMC, SIliconware, Verigy, Applied, ITRI, IME and Sematech. The next two blogs will cover significant material from this meeting.

ASE




Dr. Tong, who some say coined the term "2.5D" for the use of silicon or glass interposers with TSV, indicated that this technology “..is ready to move to the next stage” Tong expects commercialization of 2.5D chip technology to take place in two years.

Tong notes that 2.5D IC should not be regarded as a transitional integration technology. 2.5D will enable packaging of chips in the 32-22 nm nodes where the fragile mechanical stability of the low-K dielectrics used in these products will require their bonding to an intermediate silicon interposer before final placement in a standard package.







Since it can also be applied in the design of high-end multi-function-integrated ICs, as in the NEC SMAFTI 3D IC design shown below, Tong contends that it will be “… developed in parallel with 3D IC as an alternative solution”






Tong believes that commercialized products made using 2.5D IC and 3D IC technologies, including smartphones and computing applications, will hit the market in the next five years. This last comment made headlines at several news outlets [ link], which Quoted Dr. Tong as saying “ Despite tremendous progress in recent years, 3D IC with through silicon vias (TSVs) still presents significant challenges in cost, design, manufacturing, test and supply chain readiness and the technology is still three to five years away from mass production”.



After checking with Dr. Tongs colleagues in ASE I have been assured that these comments were meant to indicate that widespread use in products is still 3-5 years out but that ASE stands by the recent roadmap they shared at Semicon West this summer [ see IFTLE 9 “3D In and Around the Moscone Part 1” ] which indicates that 2.5 D readiness is imminent and full 3D for wide IO DRAM / logic bonding would be coming in the 2011 timeframe.






UMC

Shan-Chieh Chien, VP of ATD at UMC called 3D stacking with TSV the “big elephant” technology for foundries. UMC, which recently announced an alliance with Elpida and Powertech [ see IFTLE 8 “3D Infrastructure Announcements and Rumor s” ] commented that logic + wide IO DRAM stacking will occur in 2011-2012 consistent with the comments of his other Asian colleagues. UMC also sees a significant future for silicon interposers indicating that UMC will use their Cu dual damascene BEOL process for passive device and fine pitch RDL on these interposers.





We’ll finish up looking at the 2010 Semicon Taiwan 3D Forum next week



the CMOS Image Sensor Market

A new IC Insights image sensor market report forecast that CMOS image sensors sales will rise 34% in 2010 to $5.2 billion from ~ $3.9 billion in 2009. Between 2009 and 2014, CMOS image sensor sales are projected to increase at a 17% compound average growth rate (CAGR), reaching $8.3 billion by 2014. CMOS image sensors dominate portable systems applications, such as camera phones, webcams in notebook computers, and other embedded cameras in handheld products, but higher-speed CMOS imagers are also being aimed at automotive systems, medical equipment, and wireless video security networks.





For all the latest in 3D IC and Advanced Packaging stay linked to Insights From the Leading Edge………

IFTLE 17 ITRS Assembly and Packaging Roadmap

September 26, 2010 10:00 AM by Garrou

As we said last week, the 2009 ITRS roadmap (released this summer) is the first roadmap where 3D IC has become an important and integral part of both the Interconnect and the Assembly and Packaging sections. It is certainly worth our time to look at what they have to say about 3D and other advanced packaging topics. The full reports can be accessed here (Interconnect; Assembly and Packaging). In IFTLE 16 we have examined the Interconnect roadmap .

Assembly and Packaging Roadmap
Organized in nine major sections:

• Difficult Challenges
• Single Chip Packaging
• Wafer Level Packaging
• System Level Integration in Package (SiP)
• 3D Integration
• Packaging for Specialized Functions
• Advanced Packaging Elements
• Environmental Issues
• Cross-Cut Issues

Singe Chip Packaging:



Fine pitch copper wirebond has been introduced into the mainstream industry. [ see PFTLE 86 “Adv Pkging From Rimini”, 07/12/2009 ] Replacement of Au wire by Cu is the last frontier for packaging materials cost saving. They note that advanced nodes and low k materials will demand finer diameter wires for Au as well as Cu (below the 18 um being practiced today). While copper wirebond has been in use for power devices with 50 micron diameter wires and low IO counts, fine pitch Cu wirebond is a more recent development. Using fine pitch Cu wire diameters of less than 25 µm requires improvements in understanding of wire properties, IMC formation, wire bonding processes and equipment development and control for wire oxidation. Pd coated wire has been introduced to eliminate the need to for forming gas in production. The WB figure shown here is of a 18 µm Cu wirebond in a PBGA.




Some of the technology issues being addressed are bonding overhang die (i.e in a WB 3D stack like PoP and PiP ) and wire bonding on both sides of the lead frame shown below.



Flip Chip


For flip chip pitch, lower than 150 µm, has been limited by availability of high-volume cost-effective substrates and high-volume defect-free underfill processes. Application for plated wafer bumping including copper pillar wafer bumping is being expanded beyond microprocessor applications.

For applications beyond the microprocessor, graphics and game processors, FC CSP packages have been developed for applications with smaller die, lower IO array pitch and low profile small package format requirements. Primary driver has been the mobile market application, and drop test is the important reliability requirement.

Molding for FC devices
A new approach presently under investigation is underfill molding (MUF) for flip chip in package solutions. While thin packages are prone to warpage, and chips with low-κ dielectrics are more sensitive to stress low modulus molding compounds are in development to minimize the problems.


Substrates
Package substrates are both the most expensive element of packages as well as the factor limiting package performance. Advances in package substrate technology will be required to meet the cost and performance projections of the Roadmap.

Handheld consumer devices are driving ever thinner substrates and finer patterns on laminate. Total thickness has been reduced to 100 µm based on 60 µm cores in high volume manufacturing. 50 µm cores and 35 µm prepregs are available but cost is still high and improvements in handling equipment are needed to take these materials to high volume. Below 35 um thickness, new high performance low cost material is required to meet the market needs.

As copper thickness shrinks in traces and plated through holes, these features become susceptible to thermal expansion in the z-direction. CTE in z-direction must be reduced to 20 ppm/degree for core materials. The typical approach is to add filler to the resin system which typically degrades other material properties or introduces process disadvantages.

Low Κ dielectric substrates for FC-BGA are needed for high-speed transmission Incremental materials improvements enable κ~3.4 today. Materials are available with κ down to 2.8 but are still far too expensive for broad market application. There is no cost effective solution available for κ~2.5 and below. For such low κ, new reinforcement materials need to be developed as well.

Wafer Level Packaging
Wafer level packaging (WLP)is being defined as a technology in which all of the IC packaging process steps are performed at the wafer level. The original WLP definition required that all package I/O terminals be continuously located within the chip outline (fan-in design) producing a chip size package. From a systems perspective, under this definition, the limitation on WLP was how many I/O could be placed under the chip and still have a board design that can be routed.

However, new packages have recently been introduced which are “Fan-out” WLP. They are processed by placing individual sawn die into a polymer matrix that has the same form factor as the original silicon wafer. These “Reconstituted” wafers are then processed through all of the same processes that are used for “real” silicon wafers, and sawn into separate packages. The die are spaced in the polymer matrix such that there is a perimeter of polymer surrounding each placed die. This area can be used during redistribution (RDL) to “fan out” the RDL to an area larger than the original die. This allows a standard WLP solder ball pitch to be used for die that are too small in area to allow this I/O pattern without ‘growing” the die to a larger size.

Thus WLP technology can now include traditional wafer level chip size packages (WLCSP), Fan-out wafer level packages, wafer level packages with TSV, wafer level packages with Integrated Passive Devices (IPD)s. This is shown in the figure below.




In contrast to flip chip assembly, WLP assembly typically does not require underfill. Solder balls with a diameter greater than 250 µm are typically used to increase package reliability. For applications where low package height is required, smaller solder balls can be used (smallest pitches used in the market are 0.4 mm in conjunction with under-fill which would be necessary to pass typical drop tests.



SiP
The roadmap now defines SiP as “...a combination of multiple active electronic components of different functionality, assembled in a single unit, which provides multiple functions associated with a system or sub-system. A SiP may optionally contain passives, MEMS, optical components, and other packages and devices”. These may be arranged horizontally, vertically or be embedded as shown below.





3D Integration



Not much here that we haven’t already covered extensively in PFTLE and IFTLE. Below is a nice graphic from Intel showing the evolution of memory on logic (without timelines).


There is extensive discussion on chip package co design which the roadmap concludes will be necessary to reduce time to market and cost. There are also discussions on the specific requirements for opto, Rf, MEMS, automotive and LED packaging – the latter certainly being a hot topic recently. [ see PFTLE 123 “LCDs Coming to a Lighting Application Near You”, 3/18/2010 ]

One complaint I have about this document (same as the interconnect document) is that there are far to few primary references contained in the document ( 20 total) Roadmaps like this should be well documented with primary sources.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE.......

....... previous PFTLE blogs are located at www.pftle.net........

IFTLE 16 the 2009 ITRS Interconnect Roadmap - a Chance to Say “I Told You So”

September 20, 2010 10:46 AM by Garrou

The 2009 edition of the ITRS Roadmap didn’t become available till this summer. This is the first roadmap where 3D IC has become an important and integral part of both the Interconnect and the Assembly and Packaging sections. It is certainly worth our time to look at what they have to say about 3D and other related topics. The full reports can be accessed here (Interconnect; Assembly and Packaging).


The ITRS Interconnect Roadmap


Credit goes to the Interconnect committee for two reasons:
1) Unlike JEDEC [see PFTLE 128 “3D IC Standardization Begins” ]the committee list their members so you can tell exactly who was involved with generating the document. Bravo gentleman !




2) I have, in the past,been a harsh critic of the mistakes this committee made in the late 1990’s when some absurd predictions were made about where low K was going and by when [see PFTLE 44 “Upcoming 3D Integration events; Issues with the ITRS 3D Roadmap”,9/11/2008]. As you can see in the fig below, the projection the Low-K probably will not get below 2.5 with current material sets is a much more rational conclusion based on historical and current published data. This is important both to 3D and to advanced packaging of “low-K” chips. ( I say current materials new material options become available all the time for instance see "Low K Material Family Introduced by SBA Materials" 09/07/2010 SST)




Again, bravo for this open and frank discussion of past errors in projection (see figure below).






The interconnect roadmap now accepts that “reduction of the ILD к value is slowing down because of problems with manufacturability. The poor mechanical strength and adhesion properties of lower-к materials are obstructing their incorporation. Delamination and damage during CMP are major problems at early stages of development, but for mass production, the hardness and adhesion properties needed to sustain the stress imposed during assembly and packaging must also be achieved. The difficulties associated with the integration of highly porous ultra-low-κ (к ≤2) materials are becoming clearer…..the slowdown of low-к in this edition, is further reflected by delaying low-к progress by one year in light of the actual pace of deployment of new technologies.”



They also conclude that despite the fact that “…spin-on dielectrics have the benefit of less dependence on precursors than CVD, that is, one tool can handle a variety of materials, including porogen. Various spin-on low-κ materials including porous materials have been studied. However, PECVD-SiCOH has been the dominant low-κ ILD film. Non-porous spin–on materials have not been used except in some special cases. Spin-on polymer and spin-on MSQ with к ≥ 2.4 are unlikely to be used for actual logic/memory devices, consequently spin-on materials, except porous-MSQ, have been deleted from the potential solutions figure”.


Finally, a formal roadmap admission that spin-on-organic ILD has been a total failure. What was the holy grail of chemical companies in the late 1990’s, and led to career ends for several major players, is at last labeled, what some of us knew all along – a dismal failure. Those who worked with me in those years know that I was a strong opponent of spending money to develop such materials and paid a price for my failure to support certain materials. A stronger man might be able to resist saying “I told you so” …..too bad I’m not a stronger man.

……..and now onto 3D in the 2009 Interconnect Roadmap

3D Definitions and Naming


For any technology to catch on we must all be using the same language to describe it.


The 3D roadmap writers ( which I’m sure included Arkalgud, Beyne, Ramm, Pozder, Scannell and Smith among others) have chosen to go with the IMEC 3D definition set which is modeled after the JISSO hierarchy levels.








3D-P and 3D-WLP seem pretty straight forward and I can see little resistance developing about their use. 3D-P meaning stack and wire bond technology that is firmly entrenched at all the OSATS and 3D –WLP based on WLP techniques performed after chip fabrication. Basically your TSV last, vias backside technology used in production today for CMOS image sensors.



I do have some resistance to use the next two however, not because they are incorrect, but rather because they will conflict with the near decade of 3D papers already out there. They use 3D –SIC to mean the stacking and interconnecting of large and medium circuit blocks and 3D-IC to mean 3D layer connection at the local interconnect level. I think most of us have been using 3D-IC (also seen as 3D IC or 3DIC) to mean what will now be called 3D-SIC. IFTLE will begrudgingly try to conform to the new acronyms (apologizing in advance for when I will surely slip up)


Always of interest are the ITRS tables projecting what requirements will be needed at a given point in time for a given technology. I have reproduced below the tables for 3D-WLP and 3D-SIC.













All-in all a much better agreement with reality than the 2007 report which I had problems with [see PFTLE 44 “Upcoming 3D Integration events; Issues with the ITRS 3D Roadmap”,9/11/2008].




If these numbers are for first year of commercial shipment, then I find the 3D-SIC numbers a bit aggressive in terms of low end of the TSV pitch and high end of the AR. I think INTC 3 is a fair depiction of general technological capability and INTC 4 is representative of Bob Patti’s (Tezzaron) W, W2W technology.




One small general complaint about the 3D section would be the lack of references in this section of the report. For example the “Emerging Interconnect” section dealing with topics like carbon nanotubes has 93 references while the 3D section has a mere total of 5.




In the next IFTLE we will look at a look at 3D technology and other advanced packaging as seen by the Packaging and Interconnect Committee.




For all the latest of 3D technology and advanced packaging stay linked to Insights From the Leading Edge, IFTLE………………..












IFTLE 15 Sematech 3D IC Metrology Workshop

September 12, 2010 9:54 AM by Garrou

The Sematech IC 3D IC metrology workshop examined the state of non destructive metrology tools for 3D process development.

TSV metrology requirements include measurement of :
- depth
- Top and Bottom CD
- Via Pitch
- Sidewall angle (top and Bottom)


Nanda-tech
Nanda claims their optical inspection tool can be used for more than just identification of surface imperfections. The figure below shows inspection application areas in a number of 3D IC unit operations are possible.





IRTI


ITRI demonstrated the use and of a spectral reflectometer for high density through-silicon via (TSV) inspection. The non-destructive solution can measure TSV profile diameters as small as 5 um and aspect ratios greater than 13:1. The measurement precision is in the range of 0.02 um. Typical data is compared to a SEM cross section in the fig below.

Albany nano

Pofessor Kong described his studies using X-ray tomography to determine voiding in TSVs.





X-ray video showing incomplete fill in 5 um TSV are shown below.



Voids can be clearly seen after different annealing conditions without cross sectioning of the TSVs. However the technique is currently limited to small sample sizes.


McDonough of Albany presented Si stress measurements were carried out using far- field micro-Raman spectroscopy. Stress fields associated with isolated TSVs and TSV arrays were both evaluated. While results for calculated and measured were excellent for isolated TSV the TSV arrays were more complex to interpret. Ditto the anneal of stress after processing.


Olympus
Vadim Mashevsky of Olympus showed that infrared laser microscopy techniques allow imaging through bulk silicon for 3D Interconnect metrology.
Applications include:
- Overlay metrology of bonded wafers
- Overlay metrology of front side to back side wafer patterns
- Thickness metrology
- Bonded interface defect detection and defect metrology

Veeco

Novak of Veeco offers the following comments on Infrared illumination based microscopes. They :
– “See” through silicon
– Allows for alignment of stacked wafers
– Poor lateral and vertical resolution due to
– Long wavelength
– High measurement noise


White light confocal systems have:
– Good lateral resolution
– Lower vertical resolution for high aspect ratios
– Slow vertical scans
– Does not “see through silicon”


White light interferometric optical profiler
– Good lateral resolution
– Excellent vertical resolution even at high aspect ratio
– Fast vertical scans
– Mature technology, in production for decades
– Does not “see through silicon”


Below is shown 3 micron via array (vias inverted for clarity) :
Average Depth: 34.63 μm; Average width: 3.4 μm;





Suss




Suss offered the following performance metrics that metrology should seek to determine:



EVG

EVG once again shows us that alignment for Cu-Cu bonding has issues due to CTE / temp.









3D Coming Events:




There are some Major events coming this fall which are exclusively focused on 3D IC including :












For all the latest in 3D IC and advanced packaging stay linked to IFTLE....

IFTLE 14 SEMATECH 3D Stress Workshop - Part 2

September 3, 2010 9:46 AM by Garrou

The second Sematech workshop on “Stress Management for 3D ICs using Through Silicon Vias” was held in collaboration with Fraunhofer IZFP at Semicon 2010. Larry Smith, the Sematech host, has reviewed the event a few weeks ago in SST [link]. IFTLE will take a more in depth look at some of the topics/ issues brought up at the meeting. Their first workshop was covered in IFTLE 4 “Are we All Suffering from 3D Stress”

ASET / Tohohu Univ
Koyanagi-san Tohoku Univ went over the Japan ASTET consortiums Dream chip program [ we have discussed this program goals about a year ago, see PFTLE 104 “3D IC From the Land of the Rising Sun” 10/30/2009] .
Koyanagi showed the ASET roadmap which shows 3D stacked DRAM memory in 2012-2013.




Phase 3 of their demonstration device shows logic mated to memory through a Si interposer in 2012.










Of great interest to IFTLE is the ASET perspective on aspect ratio. As can be seen in the figure below ASET concurs with IFTLE that mainstream TSV will have AR ~ 2:1 - 5:1 and certainly less than 10:1.



When looking at stress in 3D wafers they also use raman spectroscopy with (+) peak shifts indicating compressive stress and (-) shifts indicating tensile stress.


IMEC


Paul Marchal of IMEC examined both the yield and reliability and the electrical impact of TSV induced stress. The fig below shows the possible components of stress in the 3D structure. Their goal is to set up a simulation flow to analyze stress and its impact in a packaged 3D chip-stack




This stress caused by a copper TSV is radial tensile because of CTE difference between Si and Cu and tangentially compressive due to crowding of Si around TSV.


Stress impact on transistor performance is shown below:




All other things being constant, smaller TSV diameter lowers stress.

IMEC’s strategy for mitigating TSV induced stress challenges:

- Process technology optimization for TSV induced stress
- Compact mechanical model, integrated in the design flow

Remaining challenges:

- combining local and global stress
- TSV impact on advanced device topologies

Qualcomm

Riko Radojcic was a busy man at Semicon speaking at both the Alchimer [ see IFTLE 11 “3D in and Around the Moscone - Part 2 ”, Aug 2010] ] and Sematech workshops . His assessment of 3D stress risks is shown in the slide below.




His proposed solutions for managing stress are outlined below:






His concept of a DFM (design for manufacturing ) process flow is shown below.






Synopsis and Mentor Graphics both gave their assessment of what it will take to implement stress impact from 3Dissues into the normal design cycle. These issues were discussed in detail previously [ see IFTLE 4 “Are we all Suffering from 3D Stress ?”, 6/2010 ]




coming soon:

- the SEMATECH metrology workshop

- the ITRS interconenct roadmap

- the ITRS assembly and packaging workshop


For all the latest in 3D ICs and advanced packaging information stay linked to IFTLE …………..






IFTLE 13 3D In and Around the Moscone Part 3

August 27, 2010 11:39 AM by Garrou

……….Finishing our look at the 3D related events at the recent Semicon West exhibition.



EVG


Markus Wimplinger , Corp Tech and IP Director, shared that 3D and TSV have been a main focus for EVG during the downturn and they feel these technologies have served them very well financially.


Wimplinger sees the only 300 mm 3D line in production is the ST Micro CIS (CMOS Image Sensor) line. Line qualification is underway right now for several customers who should be finished by 4Q 2010. He predicts that some but not all of their customers will be ready for production in the 2011-2012 timeframe and that most of them will be in Asia. Those that are furthest along actually have process ground rules out to selected key customers but have not widely distributed them yet. He also notes that W2W bonding is on the upswing again after bottoming out (vs D2W) around 12 months ago.


Verigy


Mark Allison, VP of strategic Marketing indicated that Verigy is a member of both the IME (Singapore) and ITRI (Taiwan) 3D consortia. Allison reported that some of their customer base were exerting pressure for 3D IC test solutions while others appeared to be waiting to see further clarity in the infrastructure.


Some of the TSV test challenges that they have found include:


- TSV size vs probe capabilities


- making sure the DFT (design for test) probe pads don’t add capacitance and inductance to the TSV


- handling the complex functionality of the stack


Verigy is looking into putting DFT structures on interposer which is lower cost real estate.


Equipment Heavyweights Have a Change of Heart


In the past few years PFTLE and IFTLE have documented the move of Equipment heavyweights Applied Materials and Novellus into the here-to-fore shunned area of packaging. [See PFTLE 72 “Samsung 3-D ‘Roadmap’ That Isn’t”, 4/16/2009; IFTLE “...on Finding the Beef and Finally Addressing 3D IC”, June 2010]


It wasn’t so long ago that such heavyweights snubbed their nose at the packaging market. Well, the upcoming end to scaling and Moore’s Law (as we know it) sure have turned things around [ see PFTLE “IC Consolidation, Node Scaling and 3D IC”, 03/03/2010]. Topics like 3D TSV and WLP are now the darlings of the equipment industry.


Don’t get me wrong, having the big boys set their sights on packaging and 3D with TSV is positive and developments that they come up with can only improve things for all of us in the long run. With reports that 300 mm 3D lines are going intro place around the world “as we speak” it was to be expected that both would be in “full court press” mode at Semicon – and they were.


AMAT


Dr. Randhir Thakur, executive vice president and general manager of Applied’s Silicon Systems Group announced that Applied could now offer customers “...a complete toolset for all TSV manufacturing flows encompassing etch, CVD, PVD, ECD, wafer cleaning and CMP,” said. , Applied’s Maydan Technology Center and their activity at institutes like IMEC and ITRI can only help customers develop “.. a smooth transition from R and D to volume production” as they put it.


Novellus


Novellus introduced new models of the company's VECTOR PECVD, INOVA PVD, and GxT photoresist strip systems specifically designed for WLp and 3D.


The newly-introduced SABRE 3D system addresses void-free filling, reduced copper overburden, and improved fill uniformity at higher throughputs. SABRE 3D's modular architecture can be configured with multiple plating and pre-or-post-treatment cells for a variety of packaging applications including TSV, pillar, RDL, under-bump metallization, and eutectic and lead-free micro-bumping using materials such as copper, tin, nickel, and tin silver.


The INOVA 3D PVD reportedly provides “...superior copper sidewall coverage and ultra-low defects in high aspect ratio TSVs”. The ion-induced PVD approaches reportedly reduces the manufacturing cost of consumables for the TSV PVD process step by greater than 50 percent.


The VECTOR 3D system is reportedly able to deposit low-temperature films such as silicon nitride diffusion barriers and silicon oxide isolation and passivation layers.


The G3D photoresist strip system has been designed to quickly remove thick (20-100 micron) photoresists used in the manufacture of RDLs and pillars and to achieve residue-free strip and clean of high aspect ratio TSVs.


FPGA 3D IC Rumors


With their highly repetitive structure, FPGAs have been a natural application space for 3D IC technology although no details have been announced or published anyone on the subject. Recently there have been rumors of real work going on out there that I would be remiss I not sharing with you.


In June, in his blog on chip design magazine (link), Ed Spurling reported that although Xilinx refused to comment, “a half dozen industry sources familiar with its efforts” reported that Xilinx is developing 3D for its FPGAs. IFTLE will take it one better than that and report to you that the rumored site for Xilinx activities is Samsung. No proof here either, and no confirmation from either party just the strong rumor. Although Samsung remains deathly silent on all activities concerning 3D, trust me they will be a player.


For all the latest in 3D IC and advanced packaging technology, news and rumors stay linked to Insights From the Leading Edge, IFTLE...

IFTLE 12 3D at the DAC , 3D Survey at the GSA

August 20, 2010 11:22 AM by Garrou

The importance of of suitable design tools for 3D IC have been detailed previously [ see IFTLE 9 “3D In and Around the Moscone Part 1”, Aug, 2010; PFTLE 102 The 4 Horsemen of 3D IC”,10/16 2009; PFTLE 70 “Deep in the Heart of Texas” 04/04/2009 ].





Well, it’s now becoming clear that significant EDA industry attention is being directed towards 3D IC technology.




The Design Automation Conference (DAC) which started in 1964 is clearly the preimminent technical conference / trade show, specializing in design automation. DAC is sponsored by several professional societies including IEEE Circuits and Systems Society, the IEEE Solid-State Circuits Society and the IEEE Council on Electronic Design Automation. The 2010 DAC was held in Anaheim CA.


This year, 3D IC design finally took a prominent position in the technical program. Rahul Deokar of Cadence called 2010 DAC "...a coming out party for 3D-IC design” (Link). Rick Nelson (Editor –in-chief of Electronic Design News) after attending the 3D activities at DAC writes that “the time is now for 3-D stacked die” and that “the consensus seems to be that the 3-D revolution is imminent.





Every once in awhile someone comes up with something cleaver where I think to myself “damn I wish I had thought of that” So hats off to Rick Nelson for his 3D clock (left). I’m sure I’ll be using this in future slide presentations, so in case I forget to give Rick credit, I’m doing so now in public.






In the first ever DAC panel session dedicated to 3D IC entitled "3D Stacked Die: Now or the Future?" included Myung-Soo Jang of Samsung, LC Lu of TSMC, Philippe Magarshack of ST Micro, Marchal Paul of IMEC and Riko Radojcic of Qualcomm. They all addressed the question "Are we (3D IC) there yet ?...Is it now or the future?"





There was a consensus among the speakers that commercial release of the first 3D memory on logic devices was imminent. (IFTLE feels this is a bit aggressive and continues to support the belief that prototypes may be seen in 2011 but full commercialization will not be seen till 2012)




Lu indicated that TSMC was developing 3D TSV technology with a broad focus on design, packaging and testing as well as the required foundry fabrication process. Lu indicated that n advances in design could help address current challenges related to process variations, thermal and mechanical stress.




Jang noted that design tools that work together seamlessly were required to “...speed the adoption of 3-D implementations”. Jang indicated that online video applications and mobile apps will require as much as 12.8 Gb/sec between I/O and memory with today's IC technology whereas 3-D packaging technology is expected to lower that by ~ 8X in Samsung DDRs.




Radojcic commented that 3D IC is "... not a one size fits all technology” and that it is essential to implement a Path Finding process up front in the system design in order to explore design options and make the right choices with respect to “technology, costs and die interactions”. As he has indicated at several other meetings recently [see IFTLE 11 “3D In and Around the Moscone Part 1”, Aug 2010] Radojcic feels that 3D IC ".. is all about managing choices” .




Marchal called 3D IC IMECs “man on the moon” program due to the long gestation period that was required to get all the necessary technologies into place. He prognosticated that 3D technology would arrive “ in the next two to three years," indicating that the technology has three main application drivers including “...convergence, high performance and memory systems."




DAC also held a tutorial entitled “3-D: New Dimensions in IC Design” which included instruction by Prof. Yuan Xie - Penn State, Prof. David Atienza - EPFL, Switzerland, Tanay Karnik – Intel, Paul Marchal – IMEC and Ruchir Puri - IBM .




As part of the conference the GSA (Global Semiconductor Association) held a 3D forum which reportedly had 125 attendees. Presentations were from major foundries, IDMs, EDA/IP vendors, design services and other industry organizations trying to accelerate 3D design.




For a short video of Lisa McIlrath of R3Logic discussing 3D design and design tools and their design tool “R3 Integrator” you can go here (link) .






At the Atrenta booth they conducted live demonstrations of a working 3D design flow. The design flow addresses 3D-aware high-level synthesis, early partitioning, floorplanning and multi-domain analysis. The system is the result of on-going collaboration between Atrenta, AutoESL and Qualcomm.

TSMC and Cadence

In a joint announcement at DAC, TSMC and Cadence announced that Cadence 3D-IC implementation and integrated DFM have been incorporated into TSMC Reference Flow 11.0. (link). ST Juang, senior director of Design Infrastructure Marketing at TSMC noted that . “TSMC Reference Flow 11.0 enables 3D-IC integration to become part of the mainstream flow.” Advanced 3D design capabilities including physical design and implementation; RC extraction; analysis of timing, signal integrity, IR drop, electromagnetic and thermal analysis; and physical verification are included.

With this breakthrough year at DAC, IFTLE concurrs that “The time for 3D time is now !”


The Global Semiconductor Alliance




The Global Semiconductor Alliance was formed in 1994 as the “Fabless semiconductor Association”. Their goal is to focus on initiatives that will contribute to the growth and profitability of the semiconductor industry.







In 2009 GSA’s EDA Interest Group, with representatives from EDA vendors, semiconductor firms, IC design services, research institutes and others decided to focus efforts on tools and flows to support the rapidly emerging 3-D/TSV technology. In the June 2010 issue of GSA forum, they addressed the benefits of 3D technology and described the results of an industry survey that they did on the subject.






While IFTLE agrees with their conclusion that “Accurate modeling tools and techniques, 3-D process design kits (PDKs), productive planning/partitioning tools, as well as 3-D-aware implementation and verification tools are needed. Design for 3-D testability is another challenge EDA needs to address.” Other comments like “Die stacks interconnected with TSVs are already in volume production (e.g., CMOS image sensors (CIS) in digital cameras and memory chips on top of each other to manufacture larger memory only configurations)” makes IFTLE wonder where they are getting their 3D technology industry status information. Oviously not from PFTLE or IFTLE ! for those readers know that while CIS do use TSV, they do not yet have stacked chips and while memory prototypes have been built with TSV, they are not yet commercial and certainly not is “volume production”




Lets look at some of the interesting survey conclusions that they reported. 36 semiconductor vendors responded. All expressed interest in 3-D/TSVs, and ~ 1/3 reported that they were already involved in ongoing 3-D/TSV R&D efforts. Eight of the 36 respondents are very large IC vendors, mostly fabless or fab-light, focused on the consumer and communications markets, and sell mixed-signal ICs. All achieved more than $1 billion in revenue in 2008. Seven companies generated between $100 million and $1 billion in revenue in 2008, and these companies design and manufacture mostly analog, RF and mixed-signal chips.



Mobile Internet devices (MIDs) are an obvious target segment to benefit from the space, power and cost savings that; 3-D/TSV offers. Cell phones were identified as the primary 3-D/TSV target application. Netbooks, Global Positioning System(GPS)systems and digital cameras were next in popularity.



Performance is the primary motivator for using this technology, while footprint , combined with board space savings, is a close second.






Practically all die stacks will contain at least one layer of memory.






There is also interest in integration of passives into the stack.










next week Part 3 of 3 concerning 3D activities at Semicon 2010.



For all the latest on 3D IC and advanced packaging stay linked to Insights From the Leading Edge...


Past PFTLE blogs are now available at www.pftle.net............

IFTLE 11 3D In and Around the Moscone Part 2

August 12, 2010 10:20 AM by Garrou

……….Continuing our look at the 3D related events at the recent Semicon West exhibition .

ITRI

The ITRI Ad-STAC program has been discussed previously [ see PFTLE 105 “Taiwanese Focus on 3D IC”, 11/06/2009; PFTLE 99 “3D IC at ITRI”,09/24/2009. At the Suss “3D Bonding and Thin Wafer Handling “ workshop Yu-Hua Chen, Deputy Div Director, announced that there is now a team of 150 fully engaged in 3D design, build and test.

Per their previous announcements they still appear to be on time to have their 300 mm 3D line qualified by the 4Q 2010 as shown below.













Their roadmap now shows CPU + RAM stacking and memory stacking in the 2011 / 2012 timeframe, in sinc with other Pacific rim foundries and assembly houses .







Suss




Wilfried Bair at his Suss “3D Bonding and Thin Wafer Handling “ workshop detailed the process module options for their temporary bond / debond cluster tool as shown below. He announced that their bonding chambers were now stackable to allow for smaller fab footprint. A detailed look at the Suss options has been given earlier [ see PFTLE 82 “SUSS MicroTec Bonders for Temporary and Permanent 3D Bonding Solutions”6/24/ 2009 and PFTLE 96 “Suss Microtec Thin Wafer Processing 3D IC Workshop”, 9/5/2009]




The Suss equipment is compatible with Brewer (thermal slide), 3M (laser release), HD (laser release) and TMAT (mechanical release) bond/debond processes which use different mechanics to debond the wafer from the carrier. As a result, the modules for debonding must be configured to the specific process conditions required by the adhesive.




Bair indicated that they have major wafer and interposer programs underway with both IMEC and ITRI.



Alchimer




Alchimer fresh off a cash infusion by the Panasonic Ventures Group (link) held a workshop looking a 3D status in general and their “fully wet” 3D process in particular. We have discussed their process in detail [ see PFTLE 124 “Major Moves by Alchimer “, 3/21/2010 and refs therein]




Sang Sok Lee – CEO of Lenix (Korean materials and equipment supplier to Samsung, Hynix and LG) announced the commercial availability of modular process equipment for running the Alchimer "fully wet” electrografting via fill process. The fully automated system was exclusively designed for the electro- grafting and chemical-Grafting used in the Alchimer solution. Modules include: isolation, barrier, Cu seed, via filling ( capable to 5 micron Via Diameter) and annealing.




Alchimer CTO Claudio Truzzi described the latest advances in their “fully wet” TSV line and fill process focusing on their ability to do high aspect ration TSV and their low COO.



Alchimer CTO (l) Claudio Truzzi and CEO (r) Steve Lerner




Truzzi announced that their CoO modeling using the Yole cost model shows that the wafer cost for the EMC-3D process is ~$250 per wafer vs the ~ $165 that EMC3D has previously reported (shown below) and that $70MM is needed for the equipment for such a line. We can surely expect a response from EMC3D shortly!



Yole Developpement




Jerome Baron of Yole presented their latest forcast which I have shown below by application. Their prediction that memory on logic will begin to become the driving application by 2013 is certainly consistent with current Foundry and OSAT roadmaps.






Baron offers the following (5) challenges for 3D IC to become mainstream;

- Infrastructure availability and supply chain - : availability of a second source 3D packaging service provider is critical… Additionally, key strategic alliances / partnerships between memory suppliers, Logic IDMs, Foundries and Packaging subcontractors need to be in place for 3D SiP applications involving multiple-party ICs (memory, logic, interposer…)

- I/O standardization between interfaces such as memory / logic / interposer layers is critical. Such specifications need to be defined in order to establish a standardized and flexible supply chain (e.g. of JEDEC initiative for defining LPDDR3 memory standards for 3D TSV in mobile applications)

- Thermal management and interconnect reliability: in many applications such as stacking of DRAM modules, SSD for enterprise market and memory + logic stacking applications, thermal management is certainly the biggest barrier to entry for 3D if we cannot manage to dissipate heat well through the whole package.

- Shift in the Design / Test method paradigm and system co-design: heterogeneous functions, packaging, new CAD tools (thermal and mechanical simulation), test for KGD and new design architectures are required to get the full benefits of 3D.

- and finally Cost: depending on end-product, 3D TSV manufacturing cost should be reasonable and reduced in order to make it widely occurring in cost sensitive applications.




Coming soon:

- 3D at the Design Automation Conference (DAC)

- Semicon coverage of EVG, Sematech, Novellus, Verigy

- SEMATECH 3D coverage at Semicon 2010

- A look at the new ITRS roadmaps

- A GSA survey on 3D IC …..and much more !




For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edge….










IFTLE 10 3D IC at the 2010 IEEE IITC

August 6, 2010 9:13 AM by Garrou

Coverage of Semicon 2010 will continue next week. I'm interrupting that coverage to make sure we don't forget to take a look at what occured at the IITC in June.

In 2008 PFTLE welcomed the IEEE IITC to the 3D IC bandwagon [ see PFTLE 37 “ IITC on the 3D Integration Bandwagon ”,07/07/2008 ]. In each subsequent year they have continued to expand 3D IC coverage with quality papers as is shown below for their recent June 2010 meeting.

IMEC


IMEC gave several interesting presentations at the IITC. One paper focused on the high temperature characterization of TSV capacitance, leakage and resistance. They conclude that although TSV capacitance marginally increases with the increase in temperature, TSV depletion behavior can still be exploited to reduce TSV capacitance at higher temperatures. TSV leakage measurements show that TSV oxide integrity is preserved even at higher temperatures (150C). The increase in TSV resistance matches estimations based on the positive temperature coefficient of Cu resistivity. The limited impact of temperature on measured power-delay characteristics of 2D / 3D ring oscillator circuits is due to the increase of TSV capacitance.


Another paper examined the impact of TSV - transistor proximity. Copper filled TSVs (see figure below), with a diameter of 5.2 μm and a length (height) of 22 μm, were designed and fabricated close to MOSFETs. The impact of a single TSV was examined on both PMOS and NMOS with a channel length of 0.13 μm to ~0.15 μm. For each transistor, a TSV was placed next to its active region. The distance between the edge of the channel and the TSV varied from 1.1 to 1.6 μm.








All the MOSFETs with TSVs in close proximity demonstrated normal functionality. Compared to the transistors without TSVs in proximity, no performance degradation of key transistor parameters was identified. These results show that at a minimum distance of 1.1 μm from MOSFETs, the current TSV structure has little impact on the device operation in this technology. Transistors surrounded by multiple TSVs also revealed no significant performance shift in comparison to the control cases with no TSV.


Thermal cycling between -55 and 125ºC was applied to the stacked dies. After 1000 cycles, all devices were functional and no degradation was observed with TSV proximity.


IMEC concludes that the ‘middle-TSV’ approach implemented on 130-nm CMOS technology platform has no significant impact on the electrical operation of MOSFETs and demonstrates good long-term reliability but wisely cautions that depending on technology and layout, this might not always be the case. Similar conclusions were reached previously [ see PFTLE 122, “ 3D IC at the IEEE ISSCC ”, 03/12/2010 ]


IMEC has shared information about using a polymer TSV insulation previously [ see PFTLE 125, “ 3D IC at Fort McDowell ”, 03/28/2010 ] In their most recent presentation they detail the processing for backside TSV of 50 and proposes two separate constructions for 50 and 100 µm thicknesses, (a) vs (b), as shown in the figure below.




For the 50 μm process the wafers are attached to a temporary carrier and thinned down to 50 μm. 5 μm wide ring-shaped trenches are patterned on the wafer backside and etched through the Si substrate to the BEOL pre-metal dielectric (PMD) stack. The trenches are then filled with a spin-on dielectric material. Low viscosity materials are better at void free filling of the insulation trenches.


For the 100 um process, a chamfered shape is used to avoid stress buildup at the Si corner. A sloped cavity is first etched then a second a vertical etch is done using a Bosch process IE process. Then a spin-on-dielectric from JSR is used to conformally coat the TSV. Polymer is then removed from the bottom of the hole by litho and dry etching. They indicate that this process is less likely to scale since it needs a big enough hole to do litho at the bottom of it.


Possible dimensions for these two TSV construction options are shown below.






QUALCOMM

Gu of Qualcomm shared possible integration challenges for high volume production. The interesting figure below shows the Si area in mm2 lost due to occupancy of TSVs as a function of aspect ratio for 100 um thick Si. They conclude that to maintain low Si area penalty ( i.e 2 mm2), the TSV aspect ratio should be approx 10 for 10,000 vias. This is true, but assumes the requirement of a 100 µm Si thickness.


As you may know as a reader of PFTLE [ see PFTLE 68, “ Like Swallows Returning to San Juan Capistrano ”, 03/20/2009 and PFTLE 44, “ Upcoming 3D Integration events; Issues with the ITRS 3D Roadmaps ”,09/11/2008], this author prefers a thinner Si (i.e. 30 um) which would lead to 1/3 the AR for the same lost area. Given all other things being equal lower AR always will equal lower cost.








More interesting to IFTLE are the comments Gu makes about plasma damage, namely “If the TSV is connected to a transistor during processing (which they are once the TSV are exposed from the backside – IFTLE), the plasma charge from wafer backside may damage the device gate oxide on wafer front side. Protection diodes are usually employed to protect transistor from plasma charge in the wafer front side. However, backside plasma light can be blocked from reaching the front side diode, which makes the protection diode less effective. Minimizing the plasma charge on backside process is important.” Certainly something to keep in mind.

IBM


Emma of IBM has been thinking about 3D IC and how to use them for a very long time. At IITC he gave a very interesting perspective on where we are in 3D IC integration and where we should be going.


Emma contends that in most commercial cases today, 3D is simply a packaging technique used to simplify integration. That its principle applications have been in high-volume markets where the costs of assembly are most important (such as cameras and cell phones); in markets where the physical size of the end-product is fixed (e.g., DIMMs); and in markets where both the power density and the inter-chip signal density are low. He contends that the goals of these applications are to make the end products simpler by integrating multiple components into a single stack, thereby enabling a single package and simplifying the subsequent assembly processes. It provides a way to continue the density scaling for a given footprint.


....modularity


Modularity, Emma contends, can be one of the main advantages by providing a potentially simpler design flow. For example, large IP blocks (or even layers in disparate technologies from different vendors) can be incorporated into such a stack. This requires that there be well-defined interfaces, communication protocols, and technology ground-rules that will be common to all of the individual components (i.e. standardization) . He believes that the overheads associated with such well defined infrastructures, rules, and protocols are potentially lower than those required to compose the system using a traditional 2D approach.


This has the effect of “volumizing” those subsystems, which reduces their costs and their times-to-market. In addition, he proposes that 3D can allow clocking, power delivery and control, and test-related logic to be incorporated in a more modular way.


...bandwidth


Scaling through-silicon-via (TSV) size and pitch in 3D enables high bandwidth and low latency interconnects among multiple device layers. This can enable massive internal bandwidth.


He also suggests we need to be considering system applications in which”... the logical elements of a system can be physically co-located in the {x,y} dimensions so that unprecedented bandwidth in the {z} dimension can allow the stack to do types of computation that would not be fathomable in 2-space”.


When taking a look at the constraints of 3D IC Emma offers that when combining differently constrained layers into a stack, 3D integration “...will tend to impose the combined constraints on each individual layer. Among those constraints are: (i) a shared power envelope (the amount of current drawn in any layer can impact the other layers when there are shared Power/GND TSVs), (ii) a shared thermal envelope for heat removal, and (iii) interactions between the layers in the form of noise (the reduced distances in the vertical direction, especially in thinned silicon will exacerbate noise issues). While not a major problem in low power systems, the first two constraints can be quite challenging for high-power and high power-density applications, like microprocessors”


He concludes “Today, the obvious uses for 3D are the ones in which the costs, power, interconnectivity, and profit margins are all fairly low. 3D offers some clear advantages in the future integration of systems: better volumetric density, lower raw power, smaller component count, and better modularity. But realizing these advantages requires solving a new set of problems in (literally) a new dimension.”

3D IC at the Upcoming IEEE CICC

Trying to keep you updated on what’s coming as well as what has transpired, I would be remiss if I didn’t mention the upcoming design activities at the IEEE CICC (Custom Integrated Circuits Conf) sponsored by the Solid State Circuits (SSC) and Electron Device (ED) societies.


3D veteran Rakesh Patel, who is now working on 3D IC with Global Foundries, informs IFTLE that CICC will be addressing 3D from a design perspective in their upcoming Sept 19-22 meeting in San Jose [ link ]

Their 3D forum will include:
- “3D Integration Infrastructure: Requirements to Support High Volume Production”, W. R. Bottoms, Third Millennium Test Solutions
- “3D IC – TSV Micro-bump Modeling and Design Implementation Tools”, Vassilios Gerousis, Cadence,
- “3D Packaging Evolution from an OSAT Perspective”, Raj Pendse, STATS ChipPAC
- “Challenges and Emerging Solutions for Testing TSV-Based Three-Dimensional Stacked ICs”, Erik Jan Marinissen, IMEC


In addition session 15 entitled “3D Design Considerations” will address the major 3D design topics of the day.

For all the latest on 3D IC and advanced packaging stay linked to Insights From the Leading Edge, IFTLE.....................


....Past issues of PFTLE can be accessed at http://www.pftle.net/........

IFTLE 9 3D In & Around the Moscone Part 1

August 1, 2010 11:18 AM by Garrou

I’ve seen reports of “crowded exhibit floors making it difficult to meet with companies” at Semicon West. Not sure what meeting these folks were at ? Maybe that was true in the building housing photovoltaics. As someone who has been coming to Semicon West for ~25 years I saw fewer booths and fewer attendees, fewer even then last year. Certainly nothing like the congestion that existed 10-20 years ago. I personally think we are seeing the gradual impact of our industry moving off shore. US industry is simply not as relevant as we were 20 years ago in microelectronics and there are far fewer of us in the US to attend such trade shows.








Having said that, the 3DIC activity was significant. There were two days of sessions led by Sematech, a workshop held by Alchimer, a workshop by Suss and Semicon TechXSpots sessions such as “Bridging the Gap”. We’’ll cover all of that and more, here at IFTLE,over the next few weeks.




IC Insights

Bill McClean, who correctly predicted the 2010 bull electronics market in March of 2009 [see PFTLE 67 “ IC Insights Predicts Fast Industry Rebound at IMAPS Global Business Council ”,3/15/2009 ] stated that Samsung is now spending 20% of the worlds electronics capex (~ 10B$). He sees the next downturn coming in 2013 and does not see 450 mm wafers coming till post 2015.

Proteus Biomedical

Proteus biomedical CEO Andrew Thompson during his presentartion on how microeletronics was going to affect the medical community shared the remarkable fact that the earths 7B people only 3B of them have a pair of shoes but there are 5B cell phone subscribers! That’s a lot of barefoot people talking on the phone! Another interesting

GlobalFoundries

Gregg Bartlett, Sr VP of Technology and R&D in his plenary presentation on “The Centrality of Silicon” showed 3D IC becoming essential at the 22 nm node as shown below.








Qualcomm


Qualcomm has become one of the strongest corporate advocates for 3D IC in the world. For some of their recent activity see [PFTLE 126 “ Adv Pkging at the IMAPS Device Pkging Conf ”, 04/01/2010; PFTLE 125 “3D IC at Ft McDowell”, 03/27/2010 ].


At the TechXSpots “Bridging the Gap” session Steve Bezuk of Qualcomm shared his views on how 3D fits into mobile device roadmaps. Bezuk’s comment that “The constraints of the low power, mobile market present no fundamental technical barriers to 3D TSV technologies” was music to a 3D advocates ears.


He used the PFTLE “4 Horseman of the apocalypse” concept [ see PTFLE 102, “ The 4 Horsemen of 3D IC ”, 10/16/2009 to make his point as seen below. He notes that:
- for the heterogeneous stacking designs that they are looking at today, 2D tools appear to suffice
- no thermal issues have been uncovered that do not alreadyexist for todays 2D designs
- todays sophisticated SoC test proceedures looks thik they can do he job for entry level 3D products




Bezuk added that Qualcomm is focused on copper vias middle and that detailed Qualcomm cost models are showing that the cost adder for 3D at 45 and nm should be ~ 10%.





Qualcomms Riko Radojcic, speaking at the Alchimer 3D workshop, echoed the earlier remarks of Steve Bezuk that Qualcomm can “manage the current design flow using current EDA products”. Riko, as a designer, indicated that 3D IC was a matter of managing choices and interactions (which are listed below) .







Riko indicated that thermal and mechanical stress considerations need to be incorporated into design enablement and stack design signoff.


ASE

Calvin Cheung at the Suss “3D Bonding and Thin Wafer Handling “ workshop indicated that ASE sees consumer markets driving the roadmaps towards 3D IC. Cheung indicated that facial recognition and bio-sensing for medical diagnostics were two applications that customers have indicated would be highly desirable if integrated on their PDAs.


During a panel Q&A session Chueng indicated that TSMC will be driving the initial use of interposers and that ASE was on board. “We will need interposers to bond 28 nm low K die…right now it is impossible to stack such mechanically unstable materials into a stable 3D stack” Cheung also sees interposers serving as a platform for IPD (integrated passive devices) which will allow them to get decoupling caps closer to where they are needed and that “Graphics chip sets will also require solutions where the power is not channeled through the memory”, making them another potential application for interposers. At least for the first generation products.


Rich Rice from ASE at the Bridging the Gap TechXSpot, presented the following IC cost breakdown from a recent Prismark report which indicates that Packaging and assembly constitutes 16% of total shipped silicon cost.










Amkor


Bob Lanzone, at the Suss “3D Bonding and Thin Wafer Handling “ workshop indicated that Amkor is now focusing heavily on the unit operations required to handle TSV middle wafers from foundries. They have backed off their focus on backside TSV fabrication which Bob feels is well under control. Bob says that F2F (face-to-face) CoC (chip-on-chip) technology has been qualified with Cu/Sn IMC down to 40 um pitch. Below 40 um he feels Amkor will move to some form of direct Cu-Cu bonding.

Coming soon:
- 3D IC at the IEEE IITC
- Semicon coverage of Suss, Alchimer, Yole, ITRI, EVG, Sematech, Novellus, Verigy
- 3D at the design automation conference
- A look at the ITRS new roadmap…..and much more

For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edge...     
For past PFTLE blogs go to www.pftle.net )

IFTLE 8 3D Infrastructure Announcements and Rumors

July 23, 2010 1:06 PM by Garrou

GLOBALFOUNDRIES / Tezzaron MWP Run


CMP, CMC and MOSIS have announced a multiproject wafer run for Jan 2011. MOSIS has been known for years as a supplier of prototype IC runs through its global network of foundry partners. CMP is a broker for IC and MEMS low volume production. CMC   is a non profit that supports microelectronics and Microsystems R&D in Canada.

The first two tier face-to-face bonded 3D IC run is based on Tezzarons SuperContact technology and GLOBALFOUNDRIES 130 nm CMOS. We had documented Tezzarons activities in 3D IC previously [ see PFTLE 115 "Semi Award Announced for 3-D IC Actvities ", 01/26/2010 ]

When asked about customers potentially being hesitant to work at the 130 nm node Bob Patti, CTO of Tezzaron, replied “They all need to do something different past 28 nm to differentiate themselves. Will anyone really start learning 3D at the 28 node node which will cost hundreds of millions of dollars for design or does it make more sense to start at lower cost node ?? We think likely the latter..”

Patti indicates that the multiproject run opens the door to a lot more companies and Universities to do early development capitalizing on the design kits that have already developed. “There is enough interest already to fill 2-3 reticals with parts “ According to Patti “Tezzaron is a arranging for the Si through Global foundries and will do the assembly, the backside metals and Cu  bonding “.

Elpida Announces 3D Alliance

By now you have seen the major announcement that Elpida (Japan), UMC (Taiwan) and Powertech Technologies (Taiwan) have formed an “alliance” to speed up the development of 3D chips at the 28 nm node (link ).

This makes so much sense in so many ways. Elpida has had several recent announcements indicating a strong desire to be an early player in 3D [ see PFTLE 101 “Optimism vs Reality; Semantics or Lost in Translation ”, 10/11/2009; PFTLE 97 “Ginkgo Biloba ”, 9/12/2009; “Elpida Preparing for 3D Commercialization” Semiconductor International, 3/30/2010]. UMC, meanwhile has been very silent about their 3D activity except for joining the ITRI Advanced Stacked- System Technology and Application Consortium (Ad-STAC) [ see PFTLE 99 “3D IC at ITRI ”, 9/24/2009 ]. UMC certainly needed to get more press for their activities in order to counter the attention being paid to rival TSMC [ see PFTLE 117 “On Copper Diffusion, Gettering and the Denuded Zone ” 02/06/2010; PFTLE 110 “3-D ASIP Update: TSMC & the OSATs ”, 12/23/2009 ].

Takao Adachi, CTO in charge of new technology development, has stated that ELpida wants to use it’s 3D technology to “expand beyond its DRAM business and supply systems solutions developed by stacking memory with Rf sensor and logic devices that would come from partner companies” [ see “Elpida Preparing for 3D Commercialization” Semiconductor International, 3/30/2010]. This announcement brings those goals closer to reality. Memory on Logic will enable a large number of I/O between logic and DRAM which increases the data transfer rate and reduces power consumption. Such products will be based on UMC’s foundry logic, Elpida’s DRAM and Powertechs assembly technology.

DIGITIMES reports that PTI has been discussing TSV technology with Elpida for several years and it is speculated that this alliance could lead to a partnership arrangement in the future [ link ].

UMC’s CTO reports they expect to be sampling 3D IC solutions using their 28 nm process technology “in mid 2011, with production slated for 2012”

To meet this tight time line IFTLE boldly predicts that 3D interposers it will be used to mate the UMC logic to the Elpida memory. Recall Elpida has extensive background on interposers from their previous work with NEC. [ see PFTLE 28 “NXP Proposes Passive Integration in 3D IC Stacks ”, 04/13/2008 ] We will see what really happens shortly. You can be sure you will see updates in IFTLE.

IEEE International 3D Test Workshop

PFTLE has previously listed 3D Test as one of the “4 Horseman” [ see PFTLE 102 The Four Horseman of 3-D IC Integration , 10/14/2009]. The need for standardized 3DIC test protocols have also been documented [ see: PFTLE 108, Testing 3D IC , 12/07/2009 ]

It is therefore with pleasure that IFTLE brings to your attention the 1st IEEE workshop on testing 3D Integrated Circuits “3D – Test” It will be held in conjunction with ITC (Int Test Conf) Nov.2010 in Austin. Check out this site for further details [link ]  
Leti 300 mm line

Leti has announced that it has opened a complete 300 mm fab extension dedicated to 3D applications. Equipment instillation will continue through the end of the year and an inaugural event is planned for Jan 2011. The line includes lithography, metallization, etching, dielectric dep, wet etch and packaging which will be available for Leti customers and partners.

IBM- the Rumors

In IFTLE 2 “Adv Pkging at 2010 Las Vegas ECTC ”, June 2010, I reported the speculation that a TSV containing product would be introduced into their server line. According to the rumor, the product would come off the R&D line.

There are also multiple reports that that you should be aware of, IBM will divest its fab business entirely. On May 11th EE Times reported that “rumors were rampant” that the IBM Microelectronics Division was once again up for sale and that GlobalFoundries was the reported suitor. Boris Petrov, former director of strategic marketing for Chartered has reported [link ] that the IBM hardware business currently accounts for ~ 10% of their yearly income. He sees IBM selling their fabs to Globalfoundries (backed by Abu Dhabi finances) and retaining their R&D operations. Under his scenario IBM would provide process and materials engineering for the worldwide GlobalFoundries fab operation. More if these rumors continue to develop.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE.......

remember – for access to all the previous issues of PFTLE go to www.PFTLE.net

IFTLE 7 Stacking Chips in Vegas

July 18, 2010 5:04 PM by Garrou

...Finishing our look at 3D IC papers at the 2010 ECTC in Las Vegas.


IBM

Various approaches have been studied and reported to debond the thinned wafer from the mechanical carrier wafer including thermal release, chemical dissolution and laser ablation. The laser ablation method utilizes a glass handle wafer and can be performed at room temperature for a wide range of polymeric adhesives that have proper bonding and absorption characteristics. Using controlled laser ablation parameters, IBM  reports that a 200mm wafer can be debonded after a single ablation pass for less than 1.5 minutes.

IBM / TOK

The TOK Zero Newton temporary bonding process has been discussed previously [ see PFTLE 77, Temporary Bonding for 3D Thinning and Backside Processing, May 25 2009] .


IBM and TOK have now examined the use of TOK temporary adhesives with 280 ◦C thermal stability in the TOK Zero Newton wafer handling system. They find that both a high Tg and a high softening point are necessary for thermoplastic temporary adhesives. Materials with low softening point reportedly result in as high as 13 µm “rippling” (localized wafer bow) between the die which makes backside processing “..difficult to impossible”. The new adhesive shows a Tg of 168 ◦C and a softening point of 270 ◦C which results in stability at 280 ◦C for > 1 hr and measured rippling of ~ 0.48 µm.


Temperature stability of 280 ◦C is reportedly required to sustain exposure to backside processing such as PECVD, PVD and solder reflow. It is well known that the quality of plasma deposited SiO2 degrades as processing temperatures are reduced. No off-gassing is seen from this material below 300 ◦C.


The TOK system is debond by a solvent dissolution process through a perforated carrier wafer, i.e. the thinned wafer is mounted on a film frame with the carrier perforations facing upwards, the debonding tool head is aligned with the handler and solvent is injected through the perforated carrier to gently dissolve the adhesive. Once the carrier wafer is removed, the thinned wafer on film frame is rinsed with solvent, washed and spun dry. Disolution rate is reported to be ~ 80 nm/sec.


Full 3D TSV process integration ( the full IBM process sequence for W TSV as IBM previously described in the 2006 ECTC) was carried out to show process efficacy.

CE Leti & ST Micro


Leti and ST Micro have studied the TEOS oxide deposition process in order to control parasitic capacitance for high frequency (1GHz) applications.



















TEOS based SiO2 is deposited by PECVD. The deposition temperature is 260°C due to the thermal instability of the adhesive layer between the temporary carrier and the bonded membrane for temperatures above 250-300°C. The target specifications were a dielectric constant of 4.5, a leakage current below 5 x10-8 A/cm2 at 2MV/cm and a conformality sufficient to ensure the continuity of the insulation layer at the bottom of the TSV.




O2/TEOS ratios between 0.5 and 8 were examined . The density of the deposits were (surprising to IFTLE ) all identical. The effect of gas ratio on dielectric constant and leakage current are shown below.




The impact of gas ratio on permittivity is significant. As seen in the figure below the mean value of the Dk for the SiO2 deposit strongly decreases with the gases ratio, from 10.81 for a ratio of 0.5 to 4.56 for a ratio of 8. This is associated to the reduction of –SiOH, -SiH and –OH groups in the deposit film as evidenced by FTIR analysis. Only the O2/TEOS ratio of 8 results in an acceptable leakage current of 5.1 x10-8 A/cm2.









NEC



The form factor for memory in mobile devices is limited, therefore there is strong demand for stacked die packaging use TSV to achieve improved performance, increased operating speed and minimum volume. Eliida, Oki and NEC have previously described a stacked DRAM using poly Si TSV [PFTLE 87 NEC points to Ni for Memory 3D TSV, 07/19/2009] but their high resistance interface to the back contact has limited commercialization. We have also reported that in response to these performance issues, NEC has developed electroless Ni v/ immersion Au (ENIG) process for TSV [PFTLE refs] In this ECTC publication NEC details their vias last (backside ) TSV process.


Ni was selected as the plating material because it has a high plating rate (10 to 20 µm/h) and forms a barrier against Sn-Ag solder. W was chosen as the pad metal. Thermal annealing was required to obtain sufficient adhesion to both Si and W interfaces. TSV X-sect are shown in the fig below. Layers are stacked with Cu/(SnAg) bumps. Ni bump height uniformity was an issue that had to be closely monitored. Ni TSV were 0.14 Ω vs previous results for poly silicon which were 4.1 Ω.


Stacked DRAM are shown in the fig below. No indication of commercialization was given.













Fraunhoffer IZM / NEC Schott / Schott Elect Pkging


Michael Toepper and the IZM Berlin group working with Electronic Packaging & Schott GmbH have examined the feasibility of glass interposers. They have focused on W plugs sealed into glass wafers. Rerouting metal is electroplated Au or Cu on a adhesion layer of TiWAu. Bump UBM is deposited TiW/Cu/Ni/Au. Solder balls are attached by ball drop. The higher thermal resistance of glass vs Si means thermal issues will have to be carefully watched.


For all the latest on 3D IC integration and advanced packaging stay linked to IFTLE……………..





IFTLE 6 Copper-Copper and IMC Bonding

July 11, 2010 11:11 AM by Garrou

.............before we begin I wanted to let you know that the PFTLE web page is now up at http://www.pftle.net/ . Go there and look around. All of the 128 previous blogs are now accessable, printable and searchable. More on that in the next blog................


Metal-metal bonding at the 2010 ECTC

A few weeks ago I promised to eventually bring you back to more detail on all the copper bonding studies presented at the 2010 ECTC. The categories I will include here are thermocompression Cu-Cu bonding, direct Cu bonding and IMC (intermetallic compound) formation (usually Cu-Sn-Cu bonding).

M-M direct bonding continues to be of significant interest since it is known that it is scalable as evidenced by the SOITEC SOI process which has been in mass production for a decade.

RTI Int
Research Triangle Institute detailed their study on IMC (Cu-Sn-Cu) bonding and Cu-Cu thermocompression bonding. Cu/Sn and Cu strata ready to be mated are shown in the fig below.





The RTI group is comfortable with 20 um pitch features. Anything below that and they saw slippage and subsequent misalignment when the interfaces were brought into contact. (It is felt that this is an equipment limitation not a technology limitation.) Author Reed commented that the plating of 5 um pillars “..requires very good control of the grain structure of the Sn” The Sn surface was flattened using an in situ coining process at 40 Kgf. The copper surface roughness they achieved for various processes is compared in the Table below.




Bonding was performed under a pressure of 5X10ee6 kg/msq for 3 min at 275 to 300 ₀C. Intermetallic phases at the bondline were identified by EDS as Cu3Sn. There was no Cu6Sn5 or unreacted Sn in the bond.
The Cu/Sn-Cu devices with underfill were subjected to 100 thermal cycles (+125°C to -40°C), re-probed, and then 100 hours of 85% RH / 85°C stress testing and re-probed. There were no significant changes in the electrical yield or channel resistance after thermal cycling. The average resistance was 156 Ω before and after stress testing.
Cu-Cu bonding was performed similarly at 325 ₀C and a pressure of 32.2 Kgf for 15 min. The Cu-Cu process was sensitive to any Cu dishing during the CMP with corner and edge pillars showing the most impact. During the bonding process CuO formed on the exposed Cu surfaced in the gap. Chains gave a resistance of 95.9 mΩ.
Die shear strength for both samples was ~ 8kg. For this die size, the 1x shear strength specified in MILSTD- 883E is 2.5kg. Failure occurred at the bond interface

Samsung

Samsung is one of the companies we are following closest in roder to determine the commercial progress of 3D IC. [ see PFTLE: PFTLE 122 "3-D IC at the IEEE ISSCC", 3/12/2010 and PFTLE 116 "Samsung 3-D IC Roadmap" , 02/01/2010]. At the 2010 ECTC, Samsung reported on their studies to determine the best Cu/Sn D2W (die to wafer) bonding approaches. Their test vehicle is shown in the figure below. The pads on the bottom die were Ni/Au rather than Cu. Pads are on 40 um pitch.




They examined 4 bonding schemes: (1) thermocompression (TC) with profiled heating on the bond tool and bond stage; (2) TC with constant heating on the bond tool and bond stage ; (3) fluxless local reflow bonding ( microscrubbing) and (4) flux bonding.

For TC bonding they found that bump height uniformity, TTV (total thickness variation) and wafer warpage played an important role.

1. TC Profiled heating (i.e. keeping the bonding head <>

IBM

The IBM group notes that Cu-Cu bonding is preferred due to low resistance and superior heart conduction but that high temperature and high co-planarity are needed and that there are alignment problems due to shifts caused by thermal expansion during the joining of these very small features.

Nanyang Univ & GLOBALFOUNDRIES

Nanyang Univ continues to study the use of a self assembled monolayer, SAM (i-hexanethiol) to protect copper surfaces during the Cu-Cu bonding process [ see PFTLE 103 "Show Me the Copper !", 10/23/2009 ]. Upon absorption of the SAM, the Cu surface roughness is reduces from 1.96 nm to 1.55 nm. The SAM can be desorbed from the Cu surface at ~ 200 C. While there is evidence that there is indeed Cu grain growth when samples are bonded at 250 C (vs the control without SAM) the process does not yet look ready for prime time. Unless such a process significantly decreases the surface roughness requirements of TC bonding, one appears better of using a direct bonding process.

IMEC

IMEC reported on their thermo-compression Cu-Cu bonding process for their standard Cu nails process.

The 5um diameter TSVs are etched through the PMD. A thick Ozone-TEOS SiO2 liner is conformally deposited in the TSV holes in order to isolate the TSVs from the Si bulk and to reduce the capacitive coupling. The TSVs are filled with Cu by plating and the Cu overburden is removed by CMP. Finally before final passivation, a Cu layer is added in order to connect the TSVs to the BEOL interconnect. Subsequently the wafer is mounted on a temporary carrier and thinned down to a Si-thickness of ~25 μm by a combination of grinding and CMP. At the end of this sequence, the copper of the TSVs is exposed on the wafer backside. Next the Si is recessed ~700nm by dry etching the Si with respect to the copper TSV. The result of this process is the 10μm pitch Cu nails structure shown in the figure.

In conventional Cu Back-end technologies this anneal is introduced after CMP in order to soften the Cu (through recrystallization) and thus reduce the CMP time and slurry consumption to remove the Cu overburden. However, due to the large relative dimensions of TSV, built up stress causes large Cu hillock growth from Cu TSV during the anneal at 420ºC after CMP. These protrusions are a potential threat to the IC interconnects layer, especially in case of low-k integration. This copper pumping has been discussed previously [ see PFTLE 103 "Show Me the Copper ! ", 10/23/2009 and PFTLE 125 "3D IC at Ft McDowell", 03/27/2010]

IMEC has shown that CMP of these extrusions after 20 min at 420 ◦C (in forming gas) anneal, will eliminate the protrusions from forming again during any subsequent anneals or high temperature processes.

During the Si recess process IMEC warns that Si etching with SF6 or SF6/O2 results in a highly corroded Cu surface (the protruding nail head). Addition of CF4 was necessary to achieve an acceptable Cu surface. This Cu must then be passivated (i.e Arch MS6020) in order to avoid oxidation during the thermo-compression process.

IMEC also provided further details on their Cu/Sn IMC bonding process. IMEC draws a distinction between processing done above (termed TLP) or below (termed SMB) the melting point of the Sn. When it comes to pressure (compression) requirements, TLP requires far less pressure since the molten Sn makes up for surface irregularities whereas the SMB requires higher pressure . The average roughness of their Cu and Sn plated bumps are 200 and 500 nm respectively. Peak-to valley measurements are even more revealing ( 900 and 2000 nm respectively). The rough bumps prevent Cu and Sn from having good contact and the subsequent inter-metallic formation. Therefore, bonding pressure becomes an important parameter. In fact there is a lower-limit pressure of about 20 MPa below that there is electrical connection lost. However, 150 MPa is almost the upper limit beyond which too much Sn
squeezes out leading to electrical short. Therefore, IMEC chose 50 MPa as a baseline process.

When it comes to pad cleaning NUF (no flow underfill with fluxing additives) was found to work best

CEA Leti

Lea Di Cioccio and her co-workers at CEA Leti continue reporting on their Cu-Cu direct bonding studies [ see PFTLE 58 "Fisk, Buckner and Pasta on the North End ", 12/31/2008 and PFTLE 26 "3D Practitioners Assemble at Ft McDowell ", 03/23/2008]
They define direct bonding as a process by which two mirror-polished wafers are put into contact and held together at room temperature by adhesive forces, without any additional materials.

Using test vehicles devised at NIST, their extensive electrical measurements show that the direct bonding has negligible effect on the electrical resistance of the structures they have fabricated. Daisy chains of hundreds to tens of thousands of connections were tested and showed a resistance of 79.5 milli ohm per node (bonding interface + copper lines) and a specific contact resistance of the bond ~ 22.5 milli ohm / um sq was extracted.

Their detailed study of the Cu-Cu direct bonded interface reveals a 4 nm CuO interfacial layer which begins to coalesce after 2 hrs anneal at 200 ◦C where CuO is known to become thermodynamically unstable. After a 2 hr 400 ◦C anneal the bonding interface has materials properties very close to native copper.





After a 2 hr 200 ◦C post bonding anneal bonding energy is found to be 1.14 J/m2 which is strong enough to sustain post bonding processing such as thinning. After 2 hrs at 400 ◦C a bond energy of 6.6 J/m2 was measured.

The Leti group has also examined the possibility of tungsten-tungsten direct bonding . As deposited by CVD, the W surface roughness is measured at 20 nm which is unacceptable for direct bonding. W CMP was able to bring the RMS roughness down to 0.4 nm. However, W-W bond energy , measured after 2 hr anneals at various temperatures showed very weak bonding had occurred as shown in the fig below. Even at 800 ◦C the bond energy has only reached 1.5 J/m2. Clearly this process is not yet as effective as the Cu-Cu direct bonding process.





SEMICON

- I'll be at Semicon next week gathering new information for you
Tues June 13th AM I'll be on the panel at TechXSPOT "Bridging the Gap"
Tues June 13th PM I'll be at the Suss workshop "3D Bonding and Thin Wafer Handling"
Wed June 14th PM I'll be at the Alchimer workshop "TSV Metallization that Cost 80% Less"
Hope to see a lot of you at the Sematech reception on Wed night.

For all the latest on 3-D IC and advanced packaging stay linked to Insights From the Leading Edge, IFTLE……..






IFTLE 5 2010 Date in Dresden

July 6, 2010 10:07 AM by Garrou

Design Automation and Test Europe (DATE) was recently held in Dresden. You may recall, last year DATE held a major track on 3-D integration [ see PFTLE 75, “Nice DATE ”, 05/09/2009] . Chairs Marinissen, Guillou and Van der Plas repeated the track this year with similar excellent results.





ITRI

We have recently covered 3D activities at ITRI. [see PFTLE 99, "3D IC at ITRI ”,
09/24/ 2009 and PFTLE 105, “Taiwanese Focus on 3D “, 11/06/2009 ]

At the 2010 DATE Cheng-Wen Wu from ITRI gave a plenary presentation on “What We Have Learned from SOC Is What Is Driving 3D Integration” Wu reiterated what we have seen previously [ see PFTLE 121 “IC Consolidation, Node Scaling and 3D IC ”, 03/03/2010 ] in terms of cost becoming a major obstacle in order to moving forward with future nodes.





When looking at the techniques being developed to ensure 3-D yield, the following slide is a great pictorial to how 2/4 redundancy gives much better odds of yielding a 3D stacked structure than simple TSV doubling.




Synopsys
At Semicon 2009 Ric Borges of Synopsys reported that Synopsys was ramping to provide tools in time for market adoption of 3D IC integration. [ see PFTLE 90 “MCA Delivers 3D Brightspot at Semicon ”, 7/31/2009.

At DATE Min Ni of Synopsys examined the role of thermal TSVs in a 3DIC chip stack. When comparing thermal TSV vs fluidic channels they conclude:

Thermal vias & thermal TSVs
– Pros
• can utilize existing vias and TSVs
• no additional processing steps needed
– Cons
• non-scalable due to vertical heat path.
• area penalty for extra thermal TSVs
Fluidic channels
– pros
• scalable with chip area and number of tiers
– cons
• design complexity
• reliability
• needed vertical resources

They ask the question of whether extra TSV are really needed for thermal reasons and if so when should they be added since the thermal hot spots are really not known until the routing is complete.

When looking at Impact of signal/power TSV array on temperature of 3D IC
they conclude that the maximum temperature decreases as TSVs are inserted, however, the effects saturate quickly. The proximity of thermal TSV arrays to hot spots is more critical than array size. For close proximity arrays size matters but benefits from increased array size saturates quickly. It is best to place thermal TSVs in array format to minimize area penalty, close to hotspot to maximize heat conduction. It is the boundary heat transfer coefficient that dictates the steady state temperature of chips, not the amount of TSVs.


Cascade Microtech
Thomas Thärigen of Cascade Microtech examined “3D IC Test Challenges
and Probing Concepts”. He concludes that 3D IC related DFT (design for test)
Is the key success factor for testing of 3D stacked devices, since contacting 3D circuits has several limitations (see case study later) Without considering test during design phase it will be impossible to perform effective tests on 3D stacked IC’s.

For the bottom wafer:

Probe on Regular Front-side Pads
- Function can be tested
- TSVs can not directly tested
- State of the art contact technology with regular cantilevers:
high alignment speed and high contact stability
- Available for Known Good Die/Stack Test and for Engineering Test
- Can be combined with non contact techniques
- State of the Art design techniques required for testability
- Only for the first tier

Wafer on carrier: thinned and backside completed

Probe on Extra DFT Pads
- State of the art contact technology with regular cantilevers:
high alignment speed and high contact stability
- Available for Known Good Die/Stack Test and for Engineering Test
- Limited number of regular-sized pads must be added by DFT
- Execute RPCT inside die which must be designed in by EDA
- Can be combined with non contact techniques
- Medium probe force vs. adhesive stiffness is currently under investigation

Probe on Micro Bumps
- Challenge: TSV micro-bumps small (e.g. 25μm) & numerous
- Available for KGD/KGD and Engineering Test using vertical probe cards
- Access to high pin counts = high bandwidth for tests
- Normally this TSV contacts are inter-die connects
- DFT is required to have all contacts available to execute test routines for
the single die
- Can be combined with non contact techniques
- High pin count = high probe force: Probe force vs. adhesive
stiffness is currently under investigation

Probe on TSV’s
- Challenge: TSV’s very small (e.g. 5μm) and numerous
- Only for engineering purpose, no further wafer processing possible
afterwards (bonding does not work due to probe marks)
- Use of small single tips required = only very limited number of
contacts simultaneously
- Design required to implement dedicated engineering test structures

Non contact probing is limited to pitch due to antenna issues.

The complete set of presentations can be found here:
[http://http://www.date-conference.com/conference/date10-workshop-W5

coming soon at IFTLE:

- Copper-Copper and IMC Bonding
- Stacking Chips in Vegas
- 3D IC at the IITC
- taking a look at the new ITRS roadmaps
SEMICON - I'll be at Semicon next week gathering new information for you
Tues June 13th AM I'll be on the panel at TechXSPOT "Bridging the Gap "
Tues June 13th PM I'll be at the Suss workshop "3D Bonding and Thin Wafer Handling "
Wed June 14th PM I'll be at the Alchimer workshop "TSV Metallization that Cost 80% Less"
Hope to see a lot of you at the Sematech reception on Wed night.

For all the latest on 3-D IC and advanced packaging stay linked to Insights From the Leading Edge, IFTLE……..










IFTLE 4 Are We All Suffering From 3D Stress ?

June 30, 2010 9:46 AM by Garrou

According to Geert Van der Plas of IMEC ”..TSVs, die thinning, bonding and (flip-chip) packaging result in a 3D chip-stack with built-in stress which can potentially lead to yield, electrical performance and reliability issues”

To address these issues, SEMATECH held a workshop on “Stress Management for 3D ICs” on March 16, 2010 in Albany, NY. Thanks to old friend Larry Smith for sending the pertinent info from this conference to share with you.

Synopsys

Xiaopeng Xu detailed the use of the Synopsis TCAD software to analyze 3-D structures [ link ]. The different modules in TCAD can not only be used to extract 3-D R,C & L but can also predict interconnect stress distributions from multiple stress sources and reportedly detect stress hot spots that are susceptible to debonding, voiding and cracking.

The presence of TSV appears to create more impact on the mobility of p doped Si than n doped as shown below.






Their data shows that larger TSV diameter leads to larger mobility change in Si due to larger deformation and shear stress as shown below.



Also of significant interest is the data which reveals that low-k dielectric with its inherent lower modulus results in less resistance to copper extrusion.
On Mar 09, 2010 Synopsys , and IMEC announced they have entered into a collaboration to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs).

Ansys

Kamal Karimanal of Ansys looked at techniques applicable to TSV based 3D packaging. AN example is the use of ANSYS Icepak Software to examine metal distribution and calculate temperature variations across the stack.


Qualcomm

Riko Radojcic of Qualcomm pointed out that stress management was important because for 3-D it becomes the sum of the on chip strains + the normal chip package interactions and the new 3-D TSV issues such as:

- interaction of (big) Cu TSV and surrounding devices
- µ-Bump issues with Tier 1 and Tier 2 die
- thin Si : Enhanced BEOL-FEOL + Si-package CTE Mismatch
- backside RDL : new CTE Mismatch challenges
- die to die : stress re-distribution among the stacked die
- die alignment : stress concentration among stacked die

He points out that we currently manage this on 2D chips through design rules and that it is these design rules that must be extended to 3-D stacks such as:

- Keep Out Zone Rules
- No change to device characteristics vs. ‘normal 2D Si (all devices)
- Die Stacking & Alignment Rules
- No incremental CPI effects for T1-T2 and T1-Package Interactions
- PAD and CUP Rules for µ-Bumps
- No CPI or Performance impact on either T1 or T2



Radojcic proposes an EDA solution “ that bridges package and Si design and simulation environments without forcing re-tooling from incumbent solution in either domain”

IMEC

Geert Van der Plas of IMEC indicated that insight into 3-D IC thermo-mechanical behavior requires analysis of test structures such as those shown below.





For all the latest in 3DIC and advanced packaging stay linked to Insights From the Leading Edge , IFTLE……





IFTLE 3 ......on Finding the Beef & Finally Addressing 3-D IC

June 26, 2010 9:36 AM by Garrou

This week we will catch up on some info about ALLVIA and Novellus that should be of interest to all those watching the 3-D IC evolution.

ALLVIA

To be frank with you (which you know I always try to be) I wasn’t a fan of the press releases by ALLVIA back in the winter and the resulting news stories derived from them [ for instance see: “ALLVIA offers New TSV Reliability Data”, Semi Int 01/25/2010 ].

My “beef” was “Where’s the beef ?”





[ For those of you reading this outside the US, yes I’m launching off into another of my play on words here. Several of you have asked me, when we met at conferences, to help you out when I use these play on words - so I will do now. The term “my beef” is a slang term used as a synonym for “my complaint” or “my problem”. “Where’s the beef” is a famous US television advertising quote meaning literally “where is the meat ?” The original TV commercial in 1984 featured a grey haired grandmother opening a competitors large hamburger bun, seeing a very small portion of meat and saying into the camera “Where’s the beef” (see below) ]









The headlines such as “TSV foundry ALLVIA recently completed full reliability testing of its TSVs” and “..the company is now making the data available...” led me to believe that reliability data was being disclosed but none was to be found in the “news” stories I was reading.

No indication of what was built, no indication of what tests were run and no indication as to the results of said reliability tests. Interested parties were told to contact ALLVIA. My conclusion was “Nice eye catching headline – but WHERE”S THE BEEF”, in any of the storiess that were based on this press release.

In mid March Allvia offered a webcast entitled “Silicon Interposers with TSVs and Thin-Film Capacitors”. Knowing Sergey and his team, I was willing to give them “the benefit of the doubt” .




I’m not sure how many viewers the webcast attracted, but I was in attendance, seeking "the beef", and I’m happy to say I received the data I had been looking for. I was even more sure that I had done the right thing by passing on the “headlines” in January (unlike so many others) and waiting until I had “the beef” to share with you, my readers.

This blog was then entered into que at PFTLE, but as we all know ,factors beyond my control delayed its publication until now.

So after that long introduction, lets take a look at what ALLVIA has to offer because it is still pertinent and interesting information for all of us that are interested in 3D IC.
.
As you may know, ALLVIA is currently housed in Sunnyvale where they have 6000 sq ft of clean room. This past winter they announced the acquisition of an additional 60,000 sq ft of clean room at a manufacturing facility in Portland OR. Their capability summary is detailed below. With a TSV sweet spot of 30 – 150 um they are obviously focusing on vias last-backside and interposers.




Allvia appears to be looking at the market segment that currently requires very high density laminate packages, such as Endicott Interconenct supplies, which are high density, high quality, high performance and high cost. ALLVIA claims they “...avoid the huge substrate cost increase by using a sophisticated silicon substrate on top and a cheaper organic substrate on the bottom.” Such hybrids solutions “...may cost a little bit more, but are less expensive than most non-hybrid advanced organic substrates" claims Sarastiouk.





They have examined thermal cycling of their TSV . Some of the results are shared below.

ALLVIA is also offering thin film capacitor technology integrated onto their interposers.
Reliability results for Si interposers mounted on BT substrates are shown below.





ALLVIA claims they are now ready for scaling to volume production. Good luck to them in this endeavor.


Novellus – Finally Putting 3D IC in their sights

When looking at the ECD (electrochemical deposition) landscape in relation to 3-D IC, the names Semitool, Nexx and Ebarra come to mind. They are attending 3-D conferences, making 3-D presentations and are engaged with customers on 3-D scaleups. When you look at this list one big copper plating player is noted by its absence – Novellus. Their equipment offerings include PVD and CVD Cu and W solutions and well as Cu plating technology. Their ECD copper tool “Sabre™” was one of the first on the market to meet the demands of dual damascene copper 12+ years ago.

I’m now glad to tell you that this lack of focus on 3-D IC seems to have been reversed in the last several months. Last July Novellus and the University at Albany’s College of Nanoscale Science and Engineering (CNSE) announced that they had formed a $20M partnership to conduct next-generation R&D into sub-22nm semiconductor manufacturing technology. As part of the agreement, Novellus will install three advanced thin film deposition tools-a VECTOR® plasma-enhanced chemical vapor deposition system (PECVD), a SABRE® copper electrochemical deposition system, and an ALTUS® tungsten chemical vapor deposition (CVD-W) system-at CNSE complex. It was announced that a team of Novellus researchers, located at CNSE, will be conducting leading-edge research into among other things copper fill for interconnects and copper TSV fill for 3-D IC.

On March 9th Novellus announced an advanced copper barrier-seed physical vapor deposition (PVD) process for the TSV market. The process uses Novellus’ INOVA platform to produce highly conformal copper seed films that are reportedly four times thinner than conventional PVD seed approaches. Novellus claims the process delivers excellent sidewall and bottom coverage, and enables void-free copper fill during the subsequent electroplating step. The ionized PVD process chamber causes a larger fraction of the sputtered film to land on the sidewall, which in turn results in a more conformal deposition. Novellus’ process can reportedly achieve void-free feature fill in a 60 micron deep, 10:1 aspect ratio TSV feature with vertical sidewalls using a 2000 angstrom thick copper seed layer. The conventional PVD approach requires an 8000 angstrom thick seed layer to achieve the same result. The 4X thinner TSV seed layer results in a substantial increase to system throughput and reduces the cost-of-consumables by greater than 50 percent as compared to conventional PVD approaches.

This was followed up a week later with an announced joint development program with the IBM “to design a manufacturing-worthy, copper-based, three dimensional (3- D) semiconductor Through-Silicon Via (TSV) process using Novellus' SABRE(R) copper electroplating and VECTOR(R) plasma-enhanced chemical vapor deposition (PECVD) systems.”

Novellus has reportedly developed a unique, high performance SABRE ElectrofillTM TSV process that uses Novellus hardware and chemistries to achieve void-free fill with minimal copper overburden. Copper overburden is reportedly reduced by 75 percent, allowing conventional chemical-mechanical polishing (CMP) to be used instead of custom polishing slurries. They also claim that the SABRE TSV chemistries have faster plating times, resulting in higher throughputs.
To address the requirement of lower temperature dielectrics, Novellus' VECTOR platform enables the deposition of stable dielectric films at temperatures <>

In addition, Last week Novellus introduced their XMM technology which is an inline wet etch process to reduce copper overburden on copper fill applications like TSV. XMM technology reportedly prevents chemical attack at the grain boundaries, resulting in a smooth, highly reflective copper surface. In addition, XMM technology reportedly decouples overburden deposition control from feature filling, which allows copper fill and overburden to be optimized sepertely.




With these introductions it is now obvious that Novellus is Focused on 3D IC !





For all the latest on 3D IC and advanced packaging stay linked to IFTLE.........








IFTLE 2 Adv Pkging at 2010 Las Vegas ECTC

June 20, 2010 11:30 AM by Garrou

As Jack Nicholson said in the great Stephen King horror classic “The Shining”




………………I’m baaack…………………………


Wanting to keep you up to date with recent activities, and yet not loose any of the materials that were in que two months ago when Semiconductor International went under, I will present a quick summary of announcements and rumors at the 2010 ECTC in this blog and follow with some of the blogs that were in que. I will then continue with discussions of key presentations from ECTC which should carry us into mid July and Semicon West.

They say “What goes on in Vegas stays in Vegas ”. Not so when we’re talking about 3D IC and advanced packaging…that gets reported here in IFTLE.

IEEE CPMT Takes Over Full Sponsorship of ECTC



The ECTC Conference in one form or another has been in existence since 1950. The joint sponsorship by the IEEE Components, Packaging and Manufacturing Society (CPMT) and the ECA (formerly the EIA) ended last week when IEEE bought out their long time partner. Rolf Aschenbrenner, President of IEEE CPMT commented that “.. this change should be invisible to the attendees and the ECTC program committee. We plan no changes in how the ECTC operates”



[ top l to r: Tom Reynolds, Bob Willis , Rolf Aschenbrenner,

CP Wong, Steve Bezuk, bot: Marsha Tickman, Jean Trewhella, Bill Chen ]

Fan Out WLP taking off


Most of you are familiar with fan out packaging which was developed in parallel, several years back, at Freescale (RCP) and Infineon (eWLB). During the recent hard economic times Freescale scaled back their process work and eventually licensed their process to Nepes. Infineon developed a commercialization consortium with ST Micro, ASE, STATSChipPAC and most recently Nanium (formerly Quimonda Portugal). eWLB wafers have been in mass production on 200mm lines at Infineon, ASE and STATS ChipPAC since 2009. STATS has been aggressively pursuing commercialization [ highlights from the 2010 ECTC] . STATS and Nanium are in the process of scaling up 300 mm lines. SPIL, Amkor, UTAC and others are also developing their own Fan-out wafer level packaging options.




The STATS team is pictured below at their ECTC booth where their eWLB technology was highlighted.





[from l to r: Vic Lozada, Raj Pendse, Flynn Carson, Lisa Lavin and Seung Wook Yoon]





Rumors are circulating that Freescale management, seeing the success that eWLB has been receiving, has revived their RCP process group and are looking to obtain further licenses. Rumors are that Broadcom is looking seriously at the RCP based devices. Talking with STATS who claims yields “..are already in the 90’s” for the 5-10MM units they produced in Q1 2010, it became clear that the reconfiguration step is not as simple as it looks on a power point slide. Molding compound shrinkage requires that the chips be unequally spaced across the wafer before molding compound is applied and cured and the subsequent RDL mask must match this unequal spacing – obviously. Multi die eWLB (i.e SiP ) have been qualified by the STATS team who now have stacked, (two sided) eWLB solutions in development. In any event, fan out WLP has officially taken off and will unquestionably become a major packaging option in the future.

Global Technology Development Focus Remains on 3D IC

I counted more than 25 presentations involving TSV based 3D IC. Although there were no commercial announcements, there was continued steady progress by nearly all the major players in the industry. By the way, I’m seeing more and more use of the acronym 3DIC so when doing lit searches you better use both.

I saw nothing to change my mind that the industry has narrowed process options down to vias middle (from the foundry) and vias last backside (from the OSATS). The latter mainly for devices such as CMOS image sensors which are already in full commercial production at players such as Toshiba, ST Micro and Samsung.

You can be sure that not having a source of chips with vias middle TSV is slowing down product development work. Currently, only those with their own IC fabs can gets chips containing built in TSV. While everyone is awaiting TSMC, Global Foundries and others, there appears to be a significant opportunity for R&D IC lines that can deliver test chips with vias middle TSV for developers to work with. IMEC has shown this capability, but who else out there can make such structures available ??

Please send me your info if you are or could be supporting this need.





ASE focus on 3D IC

It appears that with Cu wire bonding completely installed at ASE they can now focus on 3D IC. I’m told the EE Times article indicating that 3D at ASE was imminent [ASE Breaks Ground on New Packaging Plant] stirred significant activity at the ASE sales offices . Reports to IFTLE indicate that the new building in Kaohsiung (K 15) will indeed be used to bring all 3D equipment together, under one roof. Current D2D and D2W assembly from Chung Lee will be moved to Kaohsiung. BUT….I’m also told by those who should know, there will be no 300 mm 3D instillations till 2011 so commercial 3DIC assembly is unlikely before 2012, if then.

IBM 3D rumors

Last December at the RTI ASIP in Burlingame, IBM confirmed that there was no commercial qualified 3D line running yet. Speculation at the ECTC was that a TSV containing product will be introduced into their server line. Product would come off the R&D line. An announcement will come if performance meets expectations.

TSMC

Recent announcements of their open innovation platform indicates that TSMC is putting the pieces together to enable 3D design [TSMC adds 3D, ESL tp Platform Efforts]. Their design plans will first deal with Si interposers and it will subsequently support full 3D stacking capability. IFTLE conversations with TSMC personnel indicate that their initial roadmap announcements showing vias middle in 2011 was (as PFTLE had predicted) extremely aggressive . They view silicon interposers as a faster solution for their graphics chip customers and will switch them to full 3D stacking later. The fact that long time TSMC partner ASE will not have 300 mm equipment in place till 2011 confirms this conclusion.

3D IC Bonding

There were 10 papers at ECTC dealing with various aspects of Cu-Cu and Cu-Sn-Cu bonding including papers from IMEC, IBM, Leti, Samsung, RTI, Univ Tokyo, Nanyang Univ, / Globalfoundries. As PFTLE noted many years ago, the low COO choice of bonding techology will be limited to choices that result in mechanical and electrical connection at the same time. While the OSATS have been focused on developing Cu/Sn intermetallic technology for 3D strata bonding, there is still significant commercial interest in copper-copper bonding, perhaps due to the lower resistance connections. Cu-Cu bonding comes in white or black i.e. thermocompression or direct bonding. Actually there is enough data out there now that is becoming evident that a continuum exists between the two – shades of grey -which are dependent on the variables of surface finish, temp and pressure. A full blog will be coming up in a few weeks discussing all of this information.

Thin Film Dielectrics

Michael Toepper, Fraunhoffer IZM dielectric expert, discussed thin film polymers to a standing room only crowd and concluded that materials with the highest tensile strength and elongation were best suited for reliable fan in and fan out WLP structures.

Fan out WLP require lower temp curing materials since the chips are embedded in low temperature molding compounds. Most of the practitioners IFTLE is aware of are using JSR ( WPR 5100 series ) which are epoxy novolacs with rubber filler or the new HD Micro low cure temp PBOs ( HD 8900 series ).


The Asahi Glass group (AGC) has focused application work for their ALX polymer on fan in and fan out WLP. This material is in trials at IME, IZM and RTI and looks very promising as a BCB substitute with double the elongation and curing at 190 ◦C.

[Hijiri Kuriyama, Alan Huffman (RTI), IFTLE, Takeshi Eraguchi ]

Coming up soon:
- Finding the Beef and Addressing 3D IC
- Sematech Addresses 3D Stress
- A Date in Dresden


For all the latest on advanced packaging and 3D IC stay linked to Insights From the Leading Edge…………………..

















IFTLE 1 Insights From the Leading Edge

June 15, 2010 4:33 PM by Garrou





Like the Phoenix rising from the ashes Perspectives from the Leading Edge, PFTLE, rises from the internet black hole that it was thrust into to become Insights from the Leading Edge, IFTLE. Not much will change except the blog location. IFTLE will try to bring you weekly insight into the technical and business comings and goings in the 3DIC and IC packaging segments of our microelectronics community.







First a little background on what happened. Unbeknownst to me, Reed Elsevier the owner of Semiconductor International, owned a portfolio of magazines with a broad reach of topics. When the board decided to exit the magazine business they decided to simply close down many of them. Thus on April 16th I received a message from "headquarters" thanking me for my activities with them and terminating me and all the rest of the Semiconductor International staff. After a few seconds of shock I contacted Aaron Hand (Editor) and Dave Lammers (News Editor) and received confirmation that, indeed, Semiconductor International was no more.
I quickly tried to get back onto the web site to add some verbiage to let all of you know what had happened and tell you that I would be looking for another site to host PFTLE, but alas, I had been locked off the web page (no hard feelings, I'm sure I would have done the same thing if the situations were reversed). Having worked for a 25+ billion dollar company for most of my career, I had watched many a "big dog" get escorted off the company grounds after being told that they were terminated ....that’s simply the way it is done. Two weeks later and the web site semiconductor.net was closed and links to 3 years worth of my material now pointed into a black hole !





Emails from friends and readers began coming in questioning what was going on and pointing out that their links to my stories and blogs were now pointed no where.





The good news is that while the blogs are legally "work made for hire", my contract allows me a "worldwide, perpetual license to publish , display and distribute the works after 3 months of exclusivity". So I'm in the process of reloading the 128 blogs. By your readership of 7000 - 10,000+ hits per month, I think many of you would agree that these blogs contain a lot of worthwhile information that all of us would like to continue to access.





I will continue to refer back to these in IFTLE, and will give you all the URL to the site as soon as everything is locked down and tested. The plan is to index these so you will be able to access any and all information about a given company or topic from this new web site.





I have decided to join forces with Solid State Technology. Editor Pete Singer, while with Semiconductor International , was actually the person who gave me the opportunity to do all of this back in the summer of 2007. I look forward to working with Pete and his competent staff as IFTLE moves forward.