July 11, 2012 -- SEMICON West opened yesterday with a keynote by Shekhar Y. Borkar, Intel Fellow and director of extreme-scale technologies at Intel Corporation. Borkar focused on the energy demands of ubiquitous computing, and how technologies developed for super computers will later be adopted into smartphones. The energy demands of today's transistors, Borkar says, will not be sustainable at the exaflop data rate. At CEA-Leti's presentations later that day, researchers agreed. So how can we achieve a new power consumption paradigm?

Different transistor-level technologies can address reducing power consumption. Borkar shared Intel's 22nm 3D trigate transistor and voltage scaling at the circuit level. Scaling down the power supply voltage enables higher energy efficiency. He also discussed near-threshold voltage (NTV) operation, because energy efficiency peaks at the transistor's threshold voltage. Intel's trigate design reduces the required supply voltage and can be tuned for different thresholds. Intel has developed an experimental NTV processor to demonstrate this work. Get a look inside the trigate transistor in blogger Dick James' Intel's 22nm trigate transistor exposed

Borkar also discussed the use of systems on chip (SoC) for targeted efficiency and flexibility -- using single-purpose blocks that are extremely energy efficient along with the flexible blocks, such as microprocessor transistors, to make a chip accomodate various operations. Borkar calls this "valued performance."

Other energy-saving device architectures include stacking DRAM memory with a logic buffer to direct access to a specific page. Intel is developing this concept with Micron, calling it a Hybrid Memory Cube. Learn more from blogger Dr. Phil Garrou's The Micron Memory Cube consortium
Finally, Borkar shared some unconventional interconnect strategies for package-to-system energy savings, such as top-of-package interconnect. He stressed that circuits and interconnects should be co-optimized to maximize energy efficiency.

At CEA-Leti's research meeting, Hughes Metras, VP of strategic partnerships in North America, also projected that the next step in super computing, exascale, would be insupportably energy intensive. Leti's solutions to the energy and bandwidth demands of future computing include a planar fully depleted silicon on insulator (FDSOI) transistor architecture, silicon photonics for light-based data communication rather than electrical, and 3D integration for lower-loss and shorter interconnects.

Maud Vinet, Leti assignee at IBM, focused on planar FDSOI transistors. The benefit of planar technology is that we already have the major of the wafer processing technologies we need from bulk CMOS. The biggest change is that planar FDSOI uses extremely thin (a couple nanometers) silicon films, so extra attention must be paid at any step where silicon could be lost. The smaller gate lengths of planar FDSOI prevent parasitics, for faster operation. Back bias allows the device's threshold voltage to be tuned, a concept discussed during Intel's keynote as well. Other elements -- strain on the NFET, silicon germanium (SiGe) for the PFET -- combine in the planar FDSOI to enable 30% less power dissipation, or wasted energy, than bulk transistors.

We'll have more information from CEA-Leti's research presentatons, including the design and manufacturing perspectives on 2.5D/3D integration, on the Solid State Technology website, with a series of video interviews with the researchers. Also watch for a video interview with Intel's Borkar summarizing his keynote's main points. You'll find it all in Solid State Technology’s coverage of SEMICON West 2012.
 
-- Meredith Courtemanche, digital media editor, meredithc@pennwell.com