TI Ships 40-µm Fine Pitch Copper Pillar Flip Chip Packages
The week before Semicon West, Texas Instruments and Amkor released a joint announcement
that they were shipping parts in fine pitch copper pillar packages. Mark Lapedus at EETimes picked the story
up and added the detail that the latest OMAP processors were going out in this format.
By coincidence, Chipworks had just finished analysing TI’s Sitara AM3715 , a 45-nm applications processor with a 1-GHz ARM Cortex-A8 core and a POWERVR SGX⢠Graphics Accelerator within (it seems to be a re-purposed OMAP3630 , since the die marks are almost the same); and it turns out that it is packaged using this technology.
It had attracted my curiosity when we received the part, since the customary x-ray that we do looked odd – no wirebonds, and no C4 solder balls – so we did a section, and lo and behold, this is what we see, in Fig. 1:
This is the first time we have seen copper pillar technology since Intel adopted it a few years ago, but the style is different. Looking closer (Fig. 2), we can see that the plugs are tapered with some solder flow down the side, and it appears that the copper traces had been pre-coated with the same tin-based solder (likely SnAgCu).
The substrate is four-layer with two built-up layers (1-2-1), and the trace pitch is ~40 µm; in this section the pillars contact alternate traces, since the bond pads are staggered (Fig.3).
Amkor published two papers [1, 2] at last year’s IITC and ECTC which together seem to describe the process. Copper pillar bumps with solder caps are formed on the wafer (Fig. 4) and the wafers are thinned, in our case to ~90 µm, and then singulated.
Non-conductive paste (NCP) is pre-dispensed on the substrate and the die is thermo-compression (TC) bonded onto the substrate (Fig. 5).
One difference that we noticed in the Sitara chip was that the pillar bumps were oval, as seen in the footprints in Fig. 3. Fig. 6 shows a section at right angles to Fig. 2, and we can see the elongated profile of the pillar and the bond pad above, with a via going to a copper metal line above that. In Fig.2 we also see some leakage of the solder down the sides of the pillar, maybe a function of the TC process using an oval shape.
It appears that TI and Amkor have been using these pillar bumps for a while, since our sample was dated December last year. In the meantime, we have seen the OMAP3630 in Motorola’s new Droid X and Droid 2 phones, so they have assuredly hit high volume production.
References
[1] Lee, C., Interconnection with copper pillar bumps: Process and applications, IITC 2009, pp. 214-216.
[2] Lee, M. et al., Study of Interconnection Process for Fine Pitch Flip Chip, ECTC 2009, pp. 720-723.
By coincidence, Chipworks had just finished analysing TI’s Sitara AM3715 , a 45-nm applications processor with a 1-GHz ARM Cortex-A8 core and a POWERVR SGX⢠Graphics Accelerator within (it seems to be a re-purposed OMAP3630 , since the die marks are almost the same); and it turns out that it is packaged using this technology.
It had attracted my curiosity when we received the part, since the customary x-ray that we do looked odd – no wirebonds, and no C4 solder balls – so we did a section, and lo and behold, this is what we see, in Fig. 1:
Fig. 1 Cross-Section of Texas Instruments XAM3715
This is the first time we have seen copper pillar technology since Intel adopted it a few years ago, but the style is different. Looking closer (Fig. 2), we can see that the plugs are tapered with some solder flow down the side, and it appears that the copper traces had been pre-coated with the same tin-based solder (likely SnAgCu).
Fig. 2 Close-up of Copper Pillar Bumps
The substrate is four-layer with two built-up layers (1-2-1), and the trace pitch is ~40 µm; in this section the pillars contact alternate traces, since the bond pads are staggered (Fig.3).
Fig. 3 Plan-view Image of Bond Pads
Amkor published two papers [1, 2] at last year’s IITC and ECTC which together seem to describe the process. Copper pillar bumps with solder caps are formed on the wafer (Fig. 4) and the wafers are thinned, in our case to ~90 µm, and then singulated.
Fig. 4 Amkor Copper Pillars [1, 2]
Non-conductive paste (NCP) is pre-dispensed on the substrate and the die is thermo-compression (TC) bonded onto the substrate (Fig. 5).
Fig.5 Amkor NCP + TC Process Flow and Result [2]
One difference that we noticed in the Sitara chip was that the pillar bumps were oval, as seen in the footprints in Fig. 3. Fig. 6 shows a section at right angles to Fig. 2, and we can see the elongated profile of the pillar and the bond pad above, with a via going to a copper metal line above that. In Fig.2 we also see some leakage of the solder down the sides of the pillar, maybe a function of the TC process using an oval shape.
Fig. 6 SEM Cross-Section of Pillar Bump
It appears that TI and Amkor have been using these pillar bumps for a while, since our sample was dated December last year. In the meantime, we have seen the OMAP3630 in Motorola’s new Droid X and Droid 2 phones, so they have assuredly hit high volume production.
References
[1] Lee, C., Interconnection with copper pillar bumps: Process and applications, IITC 2009, pp. 214-216.
[2] Lee, M. et al., Study of Interconnection Process for Fine Pitch Flip Chip, ECTC 2009, pp. 720-723.
