The last few weeks have seen some announcements that finally seem to show that HKMG (high-k, metal-gate) processes other than Intel are coming into the real world.
First, on September 7, Samsung showed off an engineering sample of their 32-nm Saratoga chip at their Mobile Solutions forum. A week later on the 15th, Panasonic declared that in October they would be shipping 32-nm HKMG chips for use in Blu-ray disc players. And at the end of the month Altera launched a video on their website demonstrating the transceiver performance of their upcoming 28-nm Stratix V FPGAs, so they now have real silicon to show off, fabbed by TSMC in their gate-last HKMG process.
So things are hotting up; after almost three years, we seem to be in sight of the next HKMG product. Based on the 45-nm launches, I would put my money on Panasonic. Matsushita, as they were then, made a product announcement about having their 45-nm Uniphier chip in a Blu-ray player, and it appeared when they claimed it would. In fact it was a few days earlier than the Intel 45-nm part, back in November 2007, and remarkably we bought our Blu-ray player (in Japan) for teardown only three weeks after the part was packaged – talk about a just-in-time supply chain!
Panasonic have been remarkably quiet about their 32-nm process development, after being almost synchronous with Intel for the 65- and 45-nm generations. They have had a joint development agreement with Renesas since 1998, and in 2008 re-iterated that for 32-nm development. In September last year they announced that the joint development would continue at Renesas’ Naka site, and that they had solidified the HKMG and ultralow-k dielectric processes enough to set production dates.
Historically, Panasonic/Matsushita have appeared to focus on process shrinks for cost-reduction and SoC integration purposes, and not pushed the performance techniques as Intel did, such as enhanced strain. Changing to HKMG is a bigger stretch than shrinking a polysilicon gate process, so taking a year longer is not surprising.
The only other contender for a high-k (not metal-gate) process coming into production was NEC’s 55-nm HK variant, launched [1] some three years ago. I’ve been watching for this one since then, but while we’ve found 65-nm and 55-nm (even with embedded DRAM), we haven’t found the high-k version. I’m a bit reluctant to admit it’s vapourware, but it looks that way, especially as NEC (now Renesas) are talking of their 45-nm non-HK product.
So, we’ll see – in the meantime, Intel is steaming ahead and it looks as though they will have their 22-nm process in production on schedule in Q4 next year. We are currently anticipating their 45-nm SoC product, to see what the differences are with the 45-nm Xeons that we looked at three years ago.
Compared with previous generations, the 45-nm rollout has taken a while, particularly for some of the low-power variants. They are showing now, though, starting with Samsung/Xilinx and the higher profile A4 chips Samsung fabbed for the Apple iPad/iPods , and the UMC-fabbed TI OMAP3630 chips in the Motorola Droid series of phones.



Strangely, TSMC announced volume production of their 40LP process in November 2008 , but we have only just encountered it in a commercial product. TSMC have had well-publicised yield problems on high-end parts, but they still shipped product for Altera, AMD, nVidia, etc; it seems odd that the less complex LP product (less strain, no e-SiGe) would take longer than the GP product. It makes one wonder if leakage has been the problem with the LP variant, since it has a direct effect on battery life in mobile applications, and what is acceptable in a PC gaming system would be useless in a cell-phone.
On the CPU/GPU front, of course, 45-nm product is well established, both in PCs and other systems such as the Xbox and Playstation 3. Still, it’s been almost three years from the first 45-nm part to the latest introduction; in industry terms, maybe Moore’s law is slowing down!
[1] F. Tadashi et al., A New High-k Transistor Technology Implemented in Accordance with the 55nm Design Rule Process, NEC TECHNICAL JOURNAL Vol.1 No.5/2006 pp. 42 – 46
First, on September 7, Samsung showed off an engineering sample of their 32-nm Saratoga chip at their Mobile Solutions forum. A week later on the 15th, Panasonic declared that in October they would be shipping 32-nm HKMG chips for use in Blu-ray disc players. And at the end of the month Altera launched a video on their website demonstrating the transceiver performance of their upcoming 28-nm Stratix V FPGAs, so they now have real silicon to show off, fabbed by TSMC in their gate-last HKMG process.
So things are hotting up; after almost three years, we seem to be in sight of the next HKMG product. Based on the 45-nm launches, I would put my money on Panasonic. Matsushita, as they were then, made a product announcement about having their 45-nm Uniphier chip in a Blu-ray player, and it appeared when they claimed it would. In fact it was a few days earlier than the Intel 45-nm part, back in November 2007, and remarkably we bought our Blu-ray player (in Japan) for teardown only three weeks after the part was packaged – talk about a just-in-time supply chain!
Panasonic have been remarkably quiet about their 32-nm process development, after being almost synchronous with Intel for the 65- and 45-nm generations. They have had a joint development agreement with Renesas since 1998, and in 2008 re-iterated that for 32-nm development. In September last year they announced that the joint development would continue at Renesas’ Naka site, and that they had solidified the HKMG and ultralow-k dielectric processes enough to set production dates.
Historically, Panasonic/Matsushita have appeared to focus on process shrinks for cost-reduction and SoC integration purposes, and not pushed the performance techniques as Intel did, such as enhanced strain. Changing to HKMG is a bigger stretch than shrinking a polysilicon gate process, so taking a year longer is not surprising.
The only other contender for a high-k (not metal-gate) process coming into production was NEC’s 55-nm HK variant, launched [1] some three years ago. I’ve been watching for this one since then, but while we’ve found 65-nm and 55-nm (even with embedded DRAM), we haven’t found the high-k version. I’m a bit reluctant to admit it’s vapourware, but it looks that way, especially as NEC (now Renesas) are talking of their 45-nm non-HK product.
So, we’ll see – in the meantime, Intel is steaming ahead and it looks as though they will have their 22-nm process in production on schedule in Q4 next year. We are currently anticipating their 45-nm SoC product, to see what the differences are with the 45-nm Xeons that we looked at three years ago.
Compared with previous generations, the 45-nm rollout has taken a while, particularly for some of the low-power variants. They are showing now, though, starting with Samsung/Xilinx and the higher profile A4 chips Samsung fabbed for the Apple iPad/iPods , and the UMC-fabbed TI OMAP3630 chips in the Motorola Droid series of phones.


| Transistors from Apple/Samsung (left) and TI/UMC 45-nm Low-Power Chips |
Strangely, TSMC announced volume production of their 40LP process in November 2008 , but we have only just encountered it in a commercial product. TSMC have had well-publicised yield problems on high-end parts, but they still shipped product for Altera, AMD, nVidia, etc; it seems odd that the less complex LP product (less strain, no e-SiGe) would take longer than the GP product. It makes one wonder if leakage has been the problem with the LP variant, since it has a direct effect on battery life in mobile applications, and what is acceptable in a PC gaming system would be useless in a cell-phone.
On the CPU/GPU front, of course, 45-nm product is well established, both in PCs and other systems such as the Xbox and Playstation 3. Still, it’s been almost three years from the first 45-nm part to the latest introduction; in industry terms, maybe Moore’s law is slowing down!
[1] F. Tadashi et al., A New High-k Transistor Technology Implemented in Accordance with the 55nm Design Rule Process, NEC TECHNICAL JOURNAL Vol.1 No.5/2006 pp. 42 – 46
