Back in 2005 Samsung made an announcement
that they would be shipping eight die stacked in the same package. At the time it seemed remarkable, but we didn’t see it any time soon after that, so it got lost in the noise of other package developments and the increasing TSV (through-silicon vias) hype.
Last year we commented, in the now defunct Semiconductor International, on a 16GB Sandisk Micro-SD flash card that had nine die stacked together, thinned to a remarkable 30 µm each.
Now Samsung have delivered, in the new iPhone; our 32-GB version had one Samsung flash part within, a K9PFG08U5M (below), which their part number decoder reveals as a 256 Gb MLC (multi-level cell) NAND flash device.
One digit decodes as ‘ODP’, which isn’t clarified, but once the chip was taken off the board and x-rayed, we could see eight dies, so octal-die package seems to work. It doesn’t show up too well in plan-view, but a side-view x-ray makes it clear enough:
So, having seen the x-ray, I asked one of our lab guys to see if he could section one of the wire bond stacks that we can see in the above image. The bonds at opposite ends of the package aren’t in the same plane, so we can only get one set of bonds, but to me he did a pretty good job.
The package, including substrate, is ~0.93 mm thick, and the die stack is ~670 µm high. Die thicknesses vary from 55 – 70 µm, with the thickest die at the bottom. Thinner than the 1.4 mm announced in 2005, and not quite the 0.6 mm quoted in last year’s ‘ultra-thin’ release , but impressive nonetheless.
What surprised me, when I looked closely at the section, was how close to the top surface the top wirebond loop is – that’s 25-µm wire, so it looks to be less than 10 µm from surface – that’s minimising encapsulant for sure!
Every time we tear down something like the iPhone, it is clear that it’s not only the chip technology that makes these toys possible; they wouldn’t be the same without the parallel developments from the TAP part of the business, not to mention the software.
Still, as with the Sandisk, it poses the question: If we can build stacks of dies like this with wire bonding, will through-silicon vias ever become economic in the commodity chip arena?
Last year we commented, in the now defunct Semiconductor International, on a 16GB Sandisk Micro-SD flash card that had nine die stacked together, thinned to a remarkable 30 µm each.
Sandisk 16 GB Flash Stack in Micro-SD Card
Now Samsung have delivered, in the new iPhone; our 32-GB version had one Samsung flash part within, a K9PFG08U5M (below), which their part number decoder reveals as a 256 Gb MLC (multi-level cell) NAND flash device.
One digit decodes as ‘ODP’, which isn’t clarified, but once the chip was taken off the board and x-rayed, we could see eight dies, so octal-die package seems to work. It doesn’t show up too well in plan-view, but a side-view x-ray makes it clear enough:
So, having seen the x-ray, I asked one of our lab guys to see if he could section one of the wire bond stacks that we can see in the above image. The bonds at opposite ends of the package aren’t in the same plane, so we can only get one set of bonds, but to me he did a pretty good job.
The package, including substrate, is ~0.93 mm thick, and the die stack is ~670 µm high. Die thicknesses vary from 55 – 70 µm, with the thickest die at the bottom. Thinner than the 1.4 mm announced in 2005, and not quite the 0.6 mm quoted in last year’s ‘ultra-thin’ release , but impressive nonetheless.
What surprised me, when I looked closely at the section, was how close to the top surface the top wirebond loop is – that’s 25-µm wire, so it looks to be less than 10 µm from surface – that’s minimising encapsulant for sure!
Every time we tear down something like the iPhone, it is clear that it’s not only the chip technology that makes these toys possible; they wouldn’t be the same without the parallel developments from the TAP part of the business, not to mention the software.
Still, as with the Sandisk, it poses the question: If we can build stacks of dies like this with wire bonding, will through-silicon vias ever become economic in the commodity chip arena?
