Phil LoPiccolo, Editor-In-Chief

As the limits to continued CMOS scaling loom larger, designers are increasingly turning to multi-chip packages as a means to enhance system performance without fitting ever more devices on a single chip. To connect multiple chips in stacked-die packages, wire bonds are typically made from the edges of the chips to the substrate, but this approach still presents latency, bandwidth, and power problems, because of growing circuit density and complexity, and the resulting increased signal traffic on the interconnects.

At a recent SEMI breakfast forum, Craig Keast, head of the Advanced Silicon Technology Group and director of operations for the Microelectronics Laboratory at MIT’s Lincoln Laboratory, discussed several novel technologies for creating stacked chips that are more truly 3D-and consequently more efficient-by making multilevel connections right through the active circuitry. These techniques serve as potential solutions not only to improve system speed, increase bandwidth, and decrease power consumption, he claimed, but also to enhance mixed-material system integration and exploit best-of-breed process technologies for a range of semiconductor devices.

Describing the basic interconnect challenge, Keast noted that in traditional integrated circuits-in which multiple layers of metal interconnect are stacked on top of a single 2D layer of active circuitry-the wiring delays of global interconnects mount as device densities increase with continued scaling. Today’s high-end processors still typically run at 3.5-3.7GHz, instead of the 6GHz projected by the 2003 ITRS, Keast noted, because gate oxide scaling limitations and associated current leakage issues have hindered performance scaling.

While high-κ dielectrics and metal gates might speed up single-chip processors, wiring delays in multi-chip packages would still hinder performance. True 3D integration would avoid these delays, Keast explained, because the circle of contact a signal can reach in a 2D chip design becomes a sphere of contact in a 3D chip design, thereby dramatically increasing the number of devices that can be accessed in a single clock cycle.

Moving to 3D integration could also reduce power consumption. Keast showed that in a 90nm-node IBM microprocessor with wire lengths of up to approximately 15mm, more than 50% of the active switching power consumed by the processor was going into driving the interconnects, and >90% of that power was being consumed by the 10% longest wires. “By going to a 3D architecture, we can fold the chip onto itself, shorten the wire lengths, and have a dramatic impact not only on performance but also in reducing the power consumption,” he said.

Another benefit of 3D integration is the ability to exploit best-of-breed technologies for each layer of the stack. Rather than optimizing a single process technology to fabricate both memory and logic elements at the same time, logic and memory processes can be optimized individually and integrated with 3D interconnects to accomplish the function, Keast explained. Moreover, interconnecting circuits in this manner enables integration of mixed materials-for example, combining a layer of III-V compound semiconductor material with a layer of silicon to accomplish a particular function, he said.

Various techniques for integrating circuits in three dimensions are currently being employed. The most common approach is to use an array of bump bonds to flip-chip-interconnect two circuit layers. Another method for connecting two layers, pursued at the Research Triangle Institute in North Carolina, involves thinning a wafer to a thickness of ~30µm and gluing it down on top of the circuit layer of a completed CMOS wafer. Through-silicon vias are then etched, and each is lined with an insulator and filled with a metal plug that directly connects circuitry between the top and lower tiers.

Yet another 3D integration scheme, developed recently at MIT’s Lincoln Laboratory, can interconnect three separate layers of circuitry on fully fabricated SOI-based wafers. The technique involves inverting and aligning one wafer over another using an infrared registration technique, and then forming a low-temperature oxide bond. Handle silicon is then removed from the top-facing side of the inverted wafer in a stripping process, utilizing the buried oxide layer of the SOI wafer as an etch stop. Concentric 3D vias are then etched through both the top tier and the oxide-bonded layer all the way to the bottom-tier circuitry, and tungsten interconnect is deposited in a damascene process. The steps are repeated to add a third chip and to expose the underside of the top layer to serve as a bond pad in the final package. “When all the fabrication is done, this three-layer integrated circuit looks like a standard chip,” said Keast.

Three new technologies had to be developed to make the Lincoln Laboratory process work, said Keast. The first was a precision wafer-to-wafer alignment system to bring the wafers into close registration with one another. “There’s a potential business opportunity for people who want to build these tools,” he noted. Also required was the low-temperature oxide bonding process, and a technique to create high-density 3D vias to connect the circuit layers.

Proof-of-concept applications of Lincoln Lab’s three-tier integration process include a ring oscillator test circuit; a 1024 × 1024 imager with some one million 3D vias across the array; a photodiode laser radar; and the bonding of an SOI CMOS circuit layer to an InP handle wafer, to enable higher-density and longer-wavelength focal plane detectors. Other 3D concepts being explored by Lincoln Lab in conjunction with some 20 industry and university partners include 3D FPGAs, ASICs, flash memory, and nano-radio and RF tags.

Beyond these projects, 3D integration technologies are currently being explored by all the major semiconductor manufacturers and several start-up organizations, according to Keast. Last year Sematech started its own 3D technology program in support of member companies. He predicted that memory and processor integration would be the first to adopt full-scale production of multi-chip technology. “All of the major players are looking at this,” he noted.

One issue of concern that was raised was how to cool the 3D chips. According to Keast, heat can be dissipated by placing the hottest chip layers on the top and bottom of the stack and exploiting the thermal conductivity of the 3D vias as part of the architecture design process. He also acknowledged the significant challenge involved in 3D design, but noted that a number of preliminary 3D design kits have been developed by the likes of Mentor Graphics, Cadence, and Thermal Models, and that PTC and several universities are involved in a DARPA-sponsored program to develop 3D circuit design software.

Achieving high yield with 3D integrated circuit technology will require work in developing robust and fault-tolerant architectures, but ultimately the technology can revolutionize the design architecture of future circuits and systems, Keast believes. “Folding circuits on top of each other represents a potential solution for the interconnect delay problem facing future integrated circuits, as well as for mixed-signal, mixed process technology systems and massively parallel high-performance computing,” he said. - P.L.