Freescale Semiconductor says replacing floating polysilicon gates with nanocrystalline silicon will cut chip size and mask steps, significantly reducing the cost of its embedded flash memory products, starting with the 65nm node in 2008-2009.
The company has demonstrated a 24Mbit memory array made with 90nm process technology, using gates made of a monolayer of nanocrystals of silicon, encapsulated in a dielectric oxide. The process achieves the necessary bit-to-bit uniformity primarily by basic process control with conventional deposition tools, making ~50Å crystals arrayed at a density of ~1012/cm2. “We can find the conditions and temperatures that allow us to control the size and density pretty well,” said Bruce White, Freescale’s manager of advanced materials, memory, and interconnect.
Embedded flash is facing scaling limits, as the 9-12V high-voltage transistors typically required to reliably write and erase the charge on the conventional polysilicon gates take up an excess of valuable chip real estate, and the gates need to be encased in thick dielectrics to maintain their charge for years.
Breaking up the floating gate into lots of little separate zones means a defect in the dielectric will affect only one separate bit, and not lead to a complete loss of charge in the whole gate, so the encasing dielectric can be made significantly thinner. Also, operating voltage can be reduced to around 6V, allowing memory array size to be reduced by about 50% at 90nm. “The lower voltage also means we can commonize a lot of the processes with logic,” said White. “We can reduce [the related processes] from 10-11 masks down to 4.”
The issue now in integrating the process is to keep the crystals from oxidizing. White noted that the nanocrystalline silicon thin-film approach is one of the few candidates for next-generation flash technology that has demonstrated the reliability needed for the automotive applications of Freescale’s embedded memory.
Although Freescale is focused only on embedded applications, the technology could potentially also be used in other flash memories as well, since the very fine pitches at next-generation geometries mean the capacitance coupling between the floating gate and the control gate and thus the bit content is likely to be disturbed by surrounding features. “The nanocrystalline structure is fairly immune to interference,” said Freescale manager of memory devices Ko-Min Chang. “It also has the opportunity to extend the stand-alone roadmap, if anyone is interested.”
The company is using standard polysilicon floating gates for its 90nm generation embedded flash, so the new approach is targeted at 65nm. Researchers will next focus on figuring out the right specifications for the size of the crystals, the best encapsulating materials, the bottom oxide thickness, and the like. - P.D.