The latest etch process from Applied Materials, called AdvantEdge, targets 45nm and 32nm applications such as high-κ dielectric/metal gate and 3D transistor architectures. The new process, unveiled at Semicon West on July 12, builds on the company’s DPS etch system and DPS II process technology.
According to Thorsten Lill, GM of Applied’s conductor etch division, the tool has a wide process window that is achieved through multiple process-tuning knobs. Among the process knobs are the ability to optimize the gas-injection profile across the wafer, tune temperature across the wafer to match the optimized gas-injection profile, and tune ion flux. The first two drive CD performance in polysilicon etch; ion flux drives the etch rate.
Giving a nod to fab economics, the CD performance has been pushed to the wafer’s edge. “Chip manufacturers [today] typically utilize 90% of the wafer surface for device patterning,” noted Lill. “Extending CD performance to the edge-with a 2mm edge exclusion-equates to a 7.7% gain in available real estate. By keeping the deposition rate of the reaction by-products to the profile sidewall constant across the wafer, the CD uniformity performance is pushed to the wafer’s edge.” The company says that the process has a <3nm dimension variation reduction anywhere on the wafer.
Strain engineering at the 65nm node is targeted (e.g., SOI, SiGe, SiC, and strained PECVD spacers). At the 45nm node, applications include strained silicon with new materials for high-κ and metal gates; at the 32nm node, targets include 3D structures such as FinFETs and trigate transistors. Additionally, the company has data from Yoshio Nishi of Stanford U. that shows NAND flash density is increasing every two years, so Applied is eyeing NAND flash development at 32Gbit densities. - D.V.