STMicroelectronics is getting out of the JV chip business with Ericsson, but it's still full-steam ahead for its use of fully-depleted silicon-on-insulator (FD-SOI) technology with its partners.
The "feature-complete and silicon-verified" 28nm planar FD-SOI Technology Platform, now open for preproduction from the Crolles 300mm manufacturing facility, encompasses a full set of foundation libraries (std-cells, memory generators, I/Os, AMS IPs, and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices. Measurements on a multi-core subsystem revealed a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, according to Jean-Marc Chery, EVP/GM, digital sector, and CTO/chief manufacturing officer of STMicroelectronics.
"Post-processing wafer testing has allowed us to prove the significant performance and power advantages of FD-SOI over conventional technologies, building a cost-effective industrial solution that is available from the 28nm node," he stated. ST-Ericsson will use the FD-SOI technology in its future mobile platforms demanding high performance yet low power consumption.
Porting libraries and physical IPs from 28nm bulk CMOS to 28nm FD-SOI is "straightforward," and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI is identical to bulk, due to the absence of MOS-history-effect, ST says. FD-SOI enables production of highly energy-efficient devices (dynamic body-bias allows instant switch between high-performance mode and a very-low-leakage state), transparently for the application software, operating system, and the cache systems. FD-SOI also can operate at significant performance at low voltage with superior energy efficiency versus bulk CMOS.
Solid State Technology | Volume 56 | Issue 1 | January 2013