EUV lithography is facing several challenges, including line roughness. The cause of line roughness is complex and several approaches to prevent or smooth lines have been explored. The individual approaches are compared and a dual approach of a material and process solution is proposed.
Carlton Washburn, Brewer Science, Inc., Rolla, MO USA
As the semiconductor industry has maintained the pace set by Moore's law, it has driven development in all areas of semiconductor manufacturing. This progress can easily be tracked when looking at lithography development over time. G-line exposure tools led to i-line scanners and then to 248nm scanners. Achievements at these wavelengths, in turn, drove research into ArF technology and then to 193nm immersion lithography. Currently, the industry is focused on advancing EUV technology.
We have been developing materials for EUV lithography for the past 5 years. Through this research, many unique challenges facing EUV patterning were identified as it moves closer to production. In particular, patterning features smaller than 100nm poses an uncommon set of challenges compared to previous lithography generations. Sub-100nm technology enters the quantum realm in which most classical models break down. One reason for the departure from traditional models is that at these feature sizes, the sizes of the molecules that compose the materials become important, along with geometric changes such as surface area versus volume adjustments. It is not surprising then that feature sizes of less than 30nm have suffered from irregularities in feature width and line edge smoothness . These irregularities are commonly referred to as line width roughness and line edge roughness, or LWR and LER, respectively.
The stochastic imperfections measured as LWR and LER have a direct impact on the performance of a transistor. Most material metrology is focused on LER, whereas LWR has a larger effect on device performance. Research into the on-off current fluctuations using 45nm devices has shown a direct correlation of Ioff with LWR . As feature sizes decrease, it is expected that the impact of line roughness on device performance will increase.
Research has shown that some of the causes of LWR and LER are partly from the blur of the pattern connected to secondary electron emission, partly from the optical flare, partly from out-of-band radiation, and largely from the acid diffusion that occurs during the post-exposure step [3-5]. With several root causes, a multifaceted solution is needed.
We have seen two logical approaches to managing roughness, either preventing it or smoothing the lines after the pattern has formed. Within these two approaches, several methods are being explored, some of which are a combination of prevention and smoothing. However, industry research has focused mostly on the process of minimizing roughness before it forms. This solution appears more attractive because it is easier to avoid or minimize a problem, and usually less costly, than to troubleshoot it after the issue has materialized.
One approach to minimizing roughness during the lithography step is to use non-chemically amplified photoresists. Because much of the roughness comes from acid diffusion, it was thought that eliminating the amplification would decrease the roughness. This concept has been explored with similar conclusions. By using a non-chemically amplified photoresist, the LER was reduced. However, a large increase in dose was needed to reach the target CD size [6,7].
|An example of smoother lines from using the E2Stack AL412 assist layer coated under the photoresist. The assist layer "assists" the photoresist during the lithography patterning process to produce smoother lines.|
Our approach to minimizing line roughness is to assist the photoresist during the lithography step. This method improves line roughness by using an assist layer (AL) under the photoresist. The Figure shows top-down SEM images of a process using HMDS with photoresist, and the same photoresist with 40nm of E2Stack AL412 assist layer material. A clear improvement in performance can be seen when the assist layer is used. Researchers at imec have confirmed the benefits of this assist layer using a 20nm film thickness, with 3-sigma LER values in the range of 3.5 to 4nm .
The improvement seen by using our assist layer is apparent, but the LER must be further improved to meet the ITRS target of 2.5nm for 2012. Smoothing techniques involve ion milling, ablation, reactive ion etching, and resist reflow methods. Ion milling has shown solid improvement . Resist reflow processes have also shown promise . Smoothing processes, however, have still not delivered a solid solution.
Because no single method is delivering the needed reduction in LER, combining the benefits of an assist layer material during lithography and a smoothing process after lithography might be the dual-prong solution that is needed. By using separate steps, additional processing conditions will present options for optimization over a single step. One way this solution could work is that the assist layer would mitigate roughness during the lithography step by improving absorbance of EUV photons and secondary electrons, while post-imaging processes would burnish the lines to the needed smoothness . The LER and LWR targets would then be possible, while different processing options would be available to ease integration and process tuning.
E2Stack is a registered trademark of Brewer Science.
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Carlton Washburn received his bachelor of science in physics and mechanical engineering from Illinois College and the U. of Missouri-Rolla, respectively. Carlton is a senior applications engineer at Brewer Science, 2401 Brewer Drive, Rolla, MO 66401 USA; ph.: 573-364-0300; email email@example.com.
Solid State Technology | Volume 54 | Issue 8 | August/September 2011