Table of Contents
Solid State Technology
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Columns
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Editorial
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3D Integration: The Challenges Ahead
The potential benefits of 3D integration -- where chips are thinned, stacked and electrically connected with through-silicon vias (TSVs) – are by now well known for stacking memory and for communication chips.
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3D Integration: The Challenges Ahead
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Industry Forum
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The rule of three for CMP
Michael A. Fury, Techcet Group, LLC, Del Mar, CA
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The rule of three for CMP
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Departments
- World News
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Technology News
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3D activity at SEMICON West
At the TechXspot session on "Bridging the Gap," Steve Bezuk of Qualcomm shared his views on mobile device packaging.
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Real-time CMP monitoring tracks LPCs
With continued device geometry and new process steps comes increasing use and variety of CMP steps—e.g. through-silicon vias (TSV), ceria used for shallow-trench isolation, very thin interlayer dielectrics, colloidal silica for copper steps, copper barrier steps.
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450mm report: Standards, AMHS, platforms getting ready
In its closed-door session during SEMICON West, the International SEMATECH Manufacturing Initiative (ISMI) presented an update on the steps it is taking this year to provide the needed infrastructure, and momentum, to enable an eventual transition to the 450mm wafer size—from readiness of silicon, processes, and equipment, to factory integration issues, test wafer generation, and equipment testing methodologies.
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3D activity at SEMICON West
- Product News
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Features
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COVER ARTICLE
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Interfacial properties of Cu-Cu direct bonds for TSV integration
With varying process conditions, the quantitative analysis of the interfacial adhesion energy of Cu-Cu thermo-compression bonds was performed. Bioh Kim, et al, EV Group, Inc., Tempe, AZ USA; Eun-Jung Jang, et al, Andong National University, Andong, Korea
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Interfacial properties of Cu-Cu direct bonds for TSV integration
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TSV PROCESSES
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Process equipment readiness for through-silicon via technologies
Unit processes, integration schemes, and equipment are in place to enable development and pilot production of TSV technologies and all parts of the value chain do exist today at 300mm to enable integration technology qualification, end-product samples, and limited pilot production. Sesh Ramaswami, Applied Materials, Santa Clara, CA USA
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Convergence of 3D integrated packaging and 3D TSV ICs
As the need to integrate MEMS devices and advanced memory for sensor applications expands, work is underway to develop modules merging both mechanical and electrical devices into single, highly compact modules. Navjot Chhabra, Freescale Semiconductor, Austin, Texas, USA
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Process equipment readiness for through-silicon via technologies
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SYSTEM-IN-PACKAGE
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Achieving cost and performance goals using 3D semiconductor packaging
It has been proven that SoC and 3D multiple die packaging can significantly improve performance and the function-to-area ratio, however, one must look at the tradeoffs. Vern Solberg, STC-Madison, Madison, WI USA
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Achieving cost and performance goals using 3D semiconductor packaging
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ADVANCED PHOTOMASKS
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Overlay error components in double-patterning lithography
Wafer selection at the beginning of a process could help minimize the effects of shape changes during the wafer processing that may affect overlay error. Venkat R. Nagaswami, et al, KLA-Tencor Corp., Milpitas, CA
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Overlay error components in double-patterning lithography
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EDITORS' PICKS
TOP BLOG POSTS
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LIVE NEWS FEED
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Axcelis launches Purion XE high energy implanter
April 30, 2013
Axcelis Technologies, Inc. today announced the introduction of the Purion XE next generation single wafer high energy implanter...
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TECHNOLOGY PAPERS
Rapid Defect Indentification with Layout-Aware Diagnosis
Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are...
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Flip Chip Devices get Flat and Happy
Thin is definitely in, but what our modern flip chip devices really want is to be flat and happy! As flip chip die have become increasingly thinner in recent...
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WEBCASTS
Surface Cleaning and Preparation
This introduction requires the development of new critical and selective cleans tackling galvanic corrosion, pattern collapse both in FEOL and BEOL...
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450mm Status Report
Hear from the G450C General Manager, Paul Farrar Jr., on the current status of activities, key milestones and schedules, and imec’s senior business...
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BUYERS GUIDE
BLOGS
IFTLE 146 TSMC Apple Rumors; Gartner OSAT Mkt Numbers; Novati
Sat May 04 12:01:00 CDT 2013
IFTLE 145 GPU Roadmap, IEEE 3DIC back in SF; ConFab 2013 Pkging
Sun Apr 28 15:23:00 CDT 2013
IFTLE 144 Personnel Changes in Taiwan; Glass Usage in WLP
Sun Apr 21 10:29:00 CDT 2013
IFTLE 143 HMC status; Pkging Materials $$ now Exceed Wafer Fab Materials
Sat Apr 13 17:15:00 CDT 2013
IFTLE 142 GlobalFoundries 2.5 / 3D at 20nm; Intel Haswell GT3; UMC / SCP Prototype Details
Tue Apr 09 16:59:00 CDT 2013
Join The ConFab discussion
Tue Feb 26 11:27:00 CST 2013
Questions and answers on FD-SOI
Fri Jan 04 14:56:00 CST 2013
Present your ideas at The ConFab in 2013
Mon Nov 26 09:04:00 CST 2012
The ConFab 2013 countdown begins
Thu Aug 09 16:18:00 CDT 2012
The ConFab: Big data is here
Sun Jun 03 19:19:00 CDT 2012
Intel Foundries MEMS for Fuel Cell Start-up Nectar
Wed Jan 30 14:40:00 CST 2013
IBM surprises with 22nm details at IEDM
Wed Dec 12 04:00:00 CST 2012
Intel details 22nm trigate SoC process at IEDM
Tue Dec 11 12:23:00 CST 2012
GlobalFoundries takes on Intel with 14nm finFET “eXtreme Mobility” process
Tue Oct 02 16:22:00 CDT 2012
The Elephant Has Left the Room – 450 mm is a Go!
Tue Jul 10 09:35:00 CDT 2012
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LATEST ISSUE
05/01/2013
Volume 56, Issue 3
Article Archive for Solid State Technology.