ASM International N.V. introduced its PowerFill epitaxial silicon (epi Si) trench fill process, which enables void-free filling of deep trenches with doped, epitaxial silicon. PowerFill is an enabling process technology as it is about 3× faster than competing processes, reducing manufacturing costs and creating an additional degree of freedom in power device design (see Figure).
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| Figure Cross-section SEM image of the trench fill process at a) edge, b) half-radius, and c) center of the wafer showing good uniformity of the trench fill. The bright regions are the regions in the image where the trenches are filled by epitaxy. (Source: ASMI) 1. MSSP cure enables low wafer to wafer variation. (Source: Novellus) |
The PowerFill process was developed in response to a need to shrink the die size and on-state resistance of power management devices, Shawn Thomas, director of epi technology at ASM, told SST. "Previous generations of this structure relied on multiple implantations and blanket epi depositions to create a vertical transistor structure," he said. "The deep trench structure that is subsequently filled by in situ doped epitaxy replaces the implantation and multiple epitaxy steps of the previous generation."
The company developed and validated the technology in conjunction with IDM partners. Fairchild Semiconductor is the first end user to qualify the process for its advanced power management devices, having completed verification at its fab in Korea.
"Requirements on discrete power MOSFETs are demanding lower on-resistance, lower gate charge and higher current capability," said C.B. Son, Fairchild's director of process technology. "The Epsilon tool's performance with PowerFill has been impressive and was a significant enabling factor as we have worked to integrate this advanced trench epi process, allowing us to realize considerable cost savings as a result of its significant improvement in process throughput." — D.V.
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