Table of Contents

Solid State Technology

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  • Columns

  • Departments

    • World News

    • Tech News

      • Low-k dielectric family introduced by SBA Materials
        Since Intel's Bohr published his seminal paper on interconnect scaling in 1995, the IC community has been searching for a manufacturable low-k dielectric which could scale to below k=2.0.
      • IEDM preview: IBM Alliance simplifies pFET HKMG process
        Researchers from the IBM Alliance have developed a new germanium ion implantation process that implants Ge into the shallow silicon channel region prior to high-k/metal gate (HKMG) stack depositions.
      • IEDM: IM Flash details 25nm NAND
        Also presenting at next month's IEDM, Intel and Micron researchers will reveal the key process advances and electrical results behind their multilevel cell (MLC) 64Gb NAND flash memory technology.
      • BACUS: DFEB mask, EUV gets Brion boost
        At the Annual SPIE/BACUS Symposium 2010 (Sept. 13-16), the eBeam Initiative had several members jointly presenting the latest achievements related to an design for e-beam (DFEB) manufacturing approach, showing the effectiveness of DFEB mask technology on advanced photomasks at the 22nm node and beyond.
      • Trends and technologies for CMP in hard-disk drives
        About 40 fellow techno-geeks attended a Sept. 15 meeting of the NCCAVS CMP Users Group at SEMI headquarters in San Jose, CA, with an agenda comprising seven topics for a combination of technical, technical marketing, and marketing presentations, all with the theme of chemical mechanical planarization (CMP) for the hard-disk drive (HDD) industry.
      • Diskcon: Toshiba's bit patterning, Samsung's HDDs
        At DISKCON 2010 (Sept. 9-10, Santa Clara, CA), Toshiba Corp. presented details behind its use of bit-patterned media (BPM) to fabricate a hard disk with an areal density of 2.5TB/in2 and a practical servo pattern.
      • Researchers: SiOx OK for sub-10nm memory switch
        Researchers at Rice U. say that a new switching memory they built with electrically manipulated 10nm graphite strips doesn't actually need the graphite—good ol' reliable silicon oxide will do just fine.

  • Features

    • Cover Article

      • CMP for metal-gate integration in advanced CMOS transistors
        The needs of replacement metal gate HKMG process flows for 45nm node and below CMOS manufacturing are now being met with processes using consumables designed specifically for these steps. Paul Feeney, CMP Fellow, Cabot Microelectronics Corp., Aurora, Illinois, USA

    • Atomic Layer Deposition

      • Atomic layer deposition goes mainstream in 22nm logic technologies
        Cost-of-ownership (COO) will be a main driver for ALD equipment selection in cost-sensitive markets; and in foundry or other logic applications, equipment choice is more a mix between COO, turn-around time and process performance considerations. M. Verghese, ASM, Phoenix, AZ USA; J. W. Maes, ASM, Leuven, Belgium; N. Kobayashi, ASM, Tokyo, Japan

    • Redistribution and Fan Out

    • Advanced Substrates

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Volume 56, Issue 2
1303-sst-cvr

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