Through-silicon via (TSV) is an emerging technology for scaling, packaging, and continuing the drive to higher density and higher performance ICs. Having a smooth via surface plays an important role in the follow-up integration processes such as barrier seed layer deposition, dielectric layer deposition, and copper-fill. To achieve a smooth via surface, the standard Bosch process sacrifices the silicon etch rate and protoresist (PR) selectivity. A new etch technology gives better via profile control without sacrificing silicon etch rate, etch depth uniformity, or PR:Si selectivity.
Brad Eaton, Ajay Kumar, Sharma Pamarthy, Applied Materials, Santa Clara, CA USA
TSV is an evolution of 3D packaging, combining the best aspects of system-on-chip (SOC), where different functional blocks are fabricated on the same substrate, and system-in-package (SIP) schemes. 3D semiconductor applications include power devices (automotive technologies), image sensors, passive integration, and 3D stacked memory devices (mobile devices such as the BlackBerry and iPhone).
TSV technology links individual chips by employing vertical connections etched through a silicon wafer, which are then filled with metal to directly attach multiple die. A basic flow involves the via etched through the silicon using a deep reactive ion etching (DRIE) process. DRIE silicon etching allows for various shapes of the via profile: anisotropic, tapered, isotropic, and combinations of those shapes. This hole is then typically lined with a dielectric deposited by chemical vapor deposition (CVD). Then, much as with copper dual damascene processes, a diffusion barrier and copper seed layer are deposited by physical vapor deposition (PVD) and the hole is filled by electroplated copper.
The entry point for TSV etch varies for different device requirements depending on where in the process the vias are needed: at the front end of line (FEOL) or back end of line (BEOL). If the via are etched during the FEOL processing, the TSV scheme is via-first approach. If the via is etched during the BEOL processing, that is the via-last approach. From an integration standpoint, via depth for the via-first features is shallow compared to via-last features, with a typical depth in the range of 5–50µm. Also, via-first CDs are smaller compared to via-last application with a typical via CD in the range of 0.5 to 5µm. Additionally, via sidewall roughness required for these via features is important with a typical sidewall roughness in the range of 20 (smaller) to 100nm (larger vias).
There is an inevitable CD size vs. etch rate tradeoff. When etching smaller CDs, the etch rate is slower due to physical constraints. Therefore, etch rate requirements are less stringent for a via-fist process as compared to via-last. Via-first features call for a heavy focus on sidewall roughness. Via-last larger features have higher etch rates and more complicated film stacks. Via-last will involve etching silicon and oxide stack in one chamber to provide the lowest cost.
DRIE is the preferred technology for TSV etch as opposed to the laser process. While laser processing has lower costs, technical capabilities are limited. It causes cracks, limiting via pitch; it is a high-temperature process that causes thermal problems on the wafer (electro-migration and wafer flatness issues); it is a serial process requiring post-etch via smoothening and cleaning of the residual dust . DRIE is a “clean” technology, with a lower cost for a high number of vias that can be localized in any part of the wafer with a wide range of technology benefits.
TSV etching process approaches
For each TSV scheme (via-first and via-last), the process requirements are different. The TSV etch reactor must be flexible enough to meet these relatively different process requirements due to the wide range of via CDs and materials to etch. This study discusses key requirements for TSV etch as well as applications that employ deep silicon etch outside the regime of TSV etch.
Deep silicon etch can be performed today by two significantly different approaches. The first approach is called Bosch, or the time-multiplexed gas modulation (TMGM) process, and uses alternating deposition and etch steps for etching. The passivation of the sidewalls of the trenches is provided by heavily polymerizing chemistries, such as C4F8 and C4F6. For TSV etch applications, an etch reactor can use alternating gases that first etch silicon then deposit a protective coating on the newly etched feature. The process is repeated, making a series of isotropic etch bubbles in the silicon to form through silicon vias. The advantages of the Bosch process are high aspect ratio (AR>20:1), high photoresist (PR) selectivity, and high etch rates. The process produces a via profile with scallops and rough edges.
The second approach is called the single-step or steady-state process. In this mode, etch is dominated by halogen chemistries such as fluorine, bromine, or chlorine. Passivation of the trench sidewalls is provided by introduction of oxidizing chemistries such as O2, N2, etc. The majority of deep Si etch processes included in our study were performed using etch gases such as SF6, NF3, Cl2, and HBr. The advantages of steady-state process include smooth etched via sidewalls, high taper (especially larger CD) with possible high etch rates. The process has lower Si:PR selectivity and is harder to control undercut for deep high aspect ratio etch. Thus, the Bosch process is preferred over single-step process for many integration schemes due to the high Si:PR selectivity and higher throughput due to high AR. The expectation is that a 3D TSV etch system must have capability to run both (Bosch and single-step) process approaches.
The goal of the experiments was to evaluate the performance of the new Applied TMGM and steady-state processes on via-first and via-last applications using Applied’s TSV etch system, SilVia. All experiments were conducted in an inductively coupled plasma (ICP) etch reactor. The source has a dual coil design that enables radial control of plasma density across the wafer by varying the current ratio between the inner and outer coils. The wafer to be etched sits on a ceramic electrostatic chuck (ESC) that can operate between sub-zero to 100°C with ±<1°C wafer temperature uniformity. Effective heat transfer between the ESC and the wafer is established by flowing helium into channels between the wafer back side and the ESC surface.
The wafers used for etch process tests had small (0.54µm) to large (50µm) via features that were patterned in 2.8µm thickness I-line photoresist (PR). The pattern also contained trench lines with the same CDs with varying pitch. Each CD was laid out with different pitches to look at the impact of pitch on etch rate and selectivity. The goal of the tests was to evaluate the performance of the new TMGM process for TSV applications.
The main performance matrices evaluated were etch depth uniformity, profile control comparing the sidewall roughness performance between standard Bosch and the new TMGM processes, the power bias effects on PR:Si etch selectivity, and in situ oxide performance especially the oxide undercut.
Sidewall roughness and process control
Having a smooth sidewall profile is crucial since it affects subsequent integration steps such as liner and metal deposition. Rough surfaces are mainly caused by scalloping during the etch process. The scallops cause uneven liner/dielectric layers and voids in the copper fill as shown in Fig. 1, lefT. A smooth surface prevents choking at the top of via during subsequent fill process (Fig. 1, right).
The scallop, the cause of sidewall roughness, is attributed by isotropic lateral etch that happens during the vertical anisotropic etch (associated with standard Bosch process). To reduce the scallop size, each step time (passivation and etch) must be shortened, which consequently leads to overall slower Si etch rate. Effectively, the increase in the number of step times reduces the overall Si etch rate due to the increased number of deposition steps that cause poisoning (i.e., inhibits) of the etch reaction in the standard Bosch process. The etch rate can be reduced by 20–50% depending on energy bias in the standard Bosch process scheme.
Figure 2. Profile sensitivity to Si etch rate plot.
Another way to reduce the scallop is to make the isotropic lateral etch less sensitive during vertical etching of the via. The new Applied TMGM process aims at improving the sidewall roughness without sacrificing the Si etch rate for Bosch process by reducing the poisoning of the etch reaction (Fig. 2). This is achieved through multiplexing gas flow and RF power that minimizes lateral etch and maximizes vertical anisotropic via etch. The process factors are the reactor pressure, gas flow, gas type and RF power levels for source and bias. For example, sidewall roughness can be reduced from 280nm to below 25nm <10% loss in etch rate (Fig. 3). A 0nm scallop has demonstrated minimal impact on Si etch rate. The Applied TMGM process is less sensitive to etch reaction poisoning compared to the standard process, so the etch rates are significantly higher, even for very small or no scallop etch process for 2µm vias. The PR:Si selectivity is not changed, even with a 0nm scallop profile, using this process.
Figure 3. Applied’s TMGM process results in a) a smooth post etch sidewall, and b) a <25nm scallop, and good sidewall coverage during subsequent fill steps.
Oxide etch capability
SilVia also has an in situ oxide etch capability to enable downstream process. The process has a minimum undercut of oxide and a <40nm undercut has been demonstrated (Fig. 4).
Figure 4. In situ oxide open capability with minimum oxide using Applied’s TMGM process
Etch depth and uniformity
One percent profile non-uniformity was achieved and maintained. The non-uniformity is calculated using measurements of the CDs taken at different parts of the wafer for the same size vias. Twelve points were measured following the radial pattern. Four points were measured in level 1 (a few millimeters from the wafer’s center), same for levels 2 and 3. Level 3 is 15mm from the wafer’s edge. The twelve points were measured optically using a Lasertcec TSV300 tool. Further validation for depth measurement using a SEM was done for points closer to the wafer edge (<5mm edge exclusion) to confirm wafer edge depth uniformity. The global depth uniformity is <2% at 5mm EE. Uniform etch depth is achieved from the center to the edge of the wafer.
Bias power used in this application is relatively low when compared to the source power. High PR-Si selectivity, approximately 200:1 was achieved for I-line PR mask. This is almost as high as the 300:1 selectivity achieved using the same process with an oxide hard mask. The high PR-Si selectivity offers the opportunity to simplify the integration scheme by eliminating the need for hard masks.
There is no limit to the etch depth in this reactor. Trench depth was increased from 175 to 520µm using the same process by addition of time and no significant drop in etch rate was observed. Older reactor technologies suffer from an exponential decrease in etch rate over time, leading to erosion of the upper part of the via, manifested as widening or faceting. The reactor can be used to etch completely through the wafer if desired. A similar reactor design is used for high-volume, 750µm-deep, through-substrate etching in inkjet printer head manufacturing, a common MEMS application.
In this paper, a new TMGM process was presented. Smooth sidewall profile is critical to enable good downstream processes such as barrier layer and dielectric deposition and copper fill process. In the standard Bosch process, a tradeoff between Si etch rate and surface roughness exists; to achieve a smooth trench profile, the process step-time needs to be reduced. This reduces the isotropic lateral etching that causes the scallop, but effectively restricts the throughput of the tool. However, the new process is able to achieve smooth via sidewall with minimal degradation in Si etch rate. A smooth taper is demonstrated using a single-step process without degradation of PR:Si etch selectivity. Lastly, the process is capable of in situ oxide etch with minimal undercut of the oxide.
- “Technology & Market Analysis. 3-D TSV Interconnects Equipment & Materials — July 2008 Report,” www.yole.fr.
The authors would like to thank Jon Farr, Digvijay Raorane, and Eva Gabriel for the process development support, and Evans Baiya for developing this manuscript. SilVia is a registered trademark of Applied Materials.
Brad Eaton received his MBA from Santa Clara U. and is the global product marketing manager for Etch and Cleans group at Applied Materials, 3330 Scott Boulevard, M/S 0697, P. O. Box 58039, Santa Clara, CA 95052-8039 USA; email Brad_eaton@amat.com.
Ajay Kumar received his PhD in applied physics from the Indian Institute of Technology and is general manager of Mask Etch and Cleans group at Applied Materials.
Sharma Pamarthy received his master’s in chemical engineering from Oklahoma State U. and his MBA from Santa Clara U. and is senior process manager for TSV Etch at Applied Materials.