Wafer chip scale packaging (WCSP) eliminates conventional packaging steps such as die bonding, wire bonding, and die level flip chip attach processes. Such an approach enables faster time to market for semiconductor customers. WCSP application spaces are expanding into new areas and are segmenting based on pin count and device type. The applications of WCSP in integrating passives, discretes, RF, and memory devices are also expanding to logic ICs and MEMS. But with this growth come a number of challenges, including the impact to board-level reliability as die sizes and pin counts increase. This article will review today's challenges, along with such future trends as integration and through-silicon via (TSV) technologies.
David Stepniak, Craig Beddingfield, Chris Manack, Rajiv Dunne, Texas Instruments, Dallas, Texas, USA
Wafer-level chip scale packages come in various die sizes, ball pitch, and package thickness, which are all key enablers for WCSP.
WCSP has developed considerably over the last decade to become one of the dominant volume packages. WCSP know-how has grown from a few small niche companies to all of the large packaging subcontractors and some of the large integrated device manufacturers (IDMs) with 150mm, 200mm, as well as 300mm manufacturing capabilities (for which the demand is growing quickly and outpacing capacity). Application spaces have also grown considerably, with early adopters integrating passives and discretes.
As WCSP has matured, larger die and device types have become more diversified. Throughout this growth, a key attribute has remained: obtain reliability without utilizing underfill, which limits die size.
Ball pitch continues to be dominant at 0.5mm, with 0.4mm also in high-volume production. Bumping capability at 0.3mm has been demonstrated, but adoption is hindered by installed surface mount technology (SMT) tool set capability, substrate cost, and the potential need for underfill.
Material sets and the ability to understand process conditions have also improved. These, in turn, support improved reliability and lower cure temperatures for sensitive devices, such as memory.
The many advantages of WCSP include package footprint reductions, lower cost, improved electrical performance, and a relatively simpler construction over conventional packages. When compared to flip chip on-board components, WCSP devices do not typically require underfill. In fact, it has been demonstrated that WCSP devices on a minimum pitch of 0.4mm pitch and pin counts up to 126 do not require underfill to meet board-level reliability requirements. As WCSP sizes and pin counts continue to increase, this benefit will be challenged, but could still be maintained with the implementation of appropriate co-design tactics. As WCSP migrates to 0.3mm pitch, underfill will most likely be required to ensure that board-level reliability requirements are met. While the advantages are clear, there are a number of challenges—most notably, reliability and design.
Considerable learning has helped overcome these challenges as WCSP packages have progressed into new device types and applications. In addition to reliability and design, other primary challenges include test and wafer handling. Future opportunities, including 3D/TSV, will bring additional challenges and the need for innovative solutions.
Board-level reliability. Typically, board-level reliability (BLR) tests include temperature cycling, drop test, and bend testing. But it's also important to understand the effects on component application reliability, including use cases and mountingconfigurations (whether mounted to printed wiring board [PWB] laminate module or ceramic module). Module applications, with a mixture of via-in-pad and non-via-in-pad configurations, have presented the most difficult cases for BLR. There are, however, co-design tactics that can be used to improve BLR performance, including the stack-up structure, smart ball de-population, and unique re-distribution layer (RDL) designs.
As mobile device manufacturers drive down the height of passive components on their printed circuit boards (PCB), semiconductor providers reduce package height at the same pace. Consequently, as the solder stand-off is decreased, board-level temperature cycle performance is reduced due to the mismatching coefficient of thermal expansion between silicon and the PCB materials. In the world of low pin count analog devices, such as audio amplifiers, these global stresses are not a large concern. But as device functionality increases and more components are integrated into the same piece of silicon, the furthest ball DNP (distance from neutral point) will grow and add to the BLR risk.
Next-generation WCSPs will focus on mask set reductions for packaging. As masks are reduced, quicker time to market and package cost reductions can be achieved. This transition must be made, however, without sacrifices to electromigration and BLR. One of the layers historically thought most necessary in WCSP is the under bump metal layer, which slows the reaction between tin in the solder and the RDL. Moving forward, diffusion barrier layers will be incorporated with the re-distribution layer to eliminate the UBM layer.
|Figure 1. Wafer fab RDL (bump directly on silicon Al pad).|
Design. WCSP providers are debating where to construct the RDL needed for the routing from bond pads to the area array pattern. In the wafer fab RDL approach (Fig. 1), an extra layer of aluminum is often used for this connection. The disadvantage with this approach is that much of the top-level metal area is consumed for bump support.
|Figure 2. Bump fab RDL (bump on RDL trace).|
Most common is the bump fab RDL (Fig. 2) approach that uses copper. It allows for higher current densities and improved reliability since thicker dielectrics and metal layers can be used. Bump fab RDL also allows outgoing wafers to be split into different package types, including conventional wire-bonded packages or WCSPs, which is ideal during product development stages since quick turn samples for electrical characterization can be easily produced. When different options are available for the same device, the customer can choose a package based on thermal ratings, unit prices, and sizes that best fit their application. In the future, as wafer fabs adopt innovative copper processing solutions/structures and add thicker dielectric capabilities, the industry may re-evaluate moving the process to the fabs from separate bump facilities.
Another important challenge is understanding the impact of RDL layout on RF performance. As part of the co-design effort, the RDL must be designed while the IC is in floor plan definition—this optimizes device performance. Additionally, a structured co-design methodology must be followed to ensure electrical performance and mechanical reliability, since the location of component balls are also defined during floor planning. The use of the same silicon design in multiple package configurations (WCSP, wire-bond BGA, flip chip BGA) can also be defined during the structured co-design effort.
Along with advancements in silicon node and die shrinks, additional challenges for WCSP must be observed. WCSP integrity with low-k dielectrics, reduction of saw streets widths, and the integration of multiple fabs and assembly sites must be understood to ensure that the integrity and reliability of the WCSP package is maintained.
Test. One common concern with typical WCSP processes is the lack of a final package test. In most cases, final electrical test occurs at the wafer level after bump re-flow. Accordingly, intense visual inspections are a must in this "back-end" part of the manufacturing process, which includes laser mark, saw, and packing. As these types of packages enter into the automotive and medical sectors, process control and quality inspection systems become essential.
Wafer handling. Proper WCSP device handling is critical during the entire process—from manufacturing to qualification to SMT assembly. To ensure high assembly yields during WCSP fabrication, it's important that all process steps are automated to ensure little-to-no operator handling. During qualification, the use of temporary carriers, such as coupon boards, can help prevent damage to the device as units are handled between stress testing and electrical testing. WCSP components are typically tested in wafer form prior to singulation, which helps eliminate damage to the device that could result from handling individual packages.
Handling becomes more critical and challenging as WCSP package thickness continues to decrease to meet end-customer height requirements. Thinner WCSP packages mean thinner wafers, which can result in wafer bowing during the WCSP manufacturing process. Additionally, end customer SMT processes must be capable of handling thin silicon without damage during assembly.
As WCSP evolves, we will see the incorporation of TSV interconnect technology, which provides electrical connections from the active side to the die back-side. This capability allows the stacking of ICs or other components (MEMS, passives, etc.) to create highly integrated chip-set or system-in-package (SiP) systems.
TSV-based solutions are already in production for CMOS image sensors (CIS) and MEMS products, and there is much interest to leverage this technology for product applications requiring higher performance, lower power, heterogeneous function integration, form-factor reduction, and cost.
|Figure 3. The future of WCSP is trending toward stacked package configurations that could include a combination of WCSP with TSV,passives, MEMS and ICs.|
An illustration of a stacked WCSP package concept is shown in Fig. 3. The bottom TSV wafer could be an active WCSP device, an interposer only, or an integrated passive interposer, while the top could be an IC, a MEMS device, discrete passives, or another such device.
Since there are multiple configurations and approaches to such a stacked WCSP package assembly, a careful consideration of the integration scheme, reliability issues, business model (supply chain), and costs is required prior to choosing the product integration flow or path. For TSV fabrication, the more popular flows are the ‘via-middle' process (vias formed prior to wafer thinning within BEOL layers) and the ‘via-last' process (vias formed after completing WCSP wafer processing, including thinning).
The via-last process is the lower cost option since the TSV and back-side RDL are fabricated simultaneously. The via-middle process is advantageous for cases requiring fine-pitch and smaller via diameter; these requirements could be for performance and to enable die size entitlement. Subsequently, the assembly of the components to be stacked could involve attach using wire-bonding, SMT, or flip chip processes, followed by an overmolding step (if necessary). Another possibility, the final package could be a stand-alone TSV-WCSP only, on which components will be stacked later similar to a POP (package-on-package), or simply embedded inside a substrate or PCB laminate.
Among key development areas in a stacked WCSP manufacturing flow are TSV etch and plating steps (partial or complete fill), the component stacking interconnect and assembly approach (depends on the thermal budget), selection of an overmold material that will result in minimal wafer-level and package-level warpage, selection of a carrier wafer bonding adhesive compatible with the oxide deposition and stacked component assembly processes, and handling and shipping of thin unmolded or molded wafers or thin dies.
|Low form factor and high achievable pin count forWCSPs are enabling new application opportunities.|
These all require additional capital for a carrier wafer support system for bonding/de-bonding the device wafer or stacked wafer sub-assembly, chip-to-wafer (C2W) pick-and-place or flip chip bonding machines, wafer-level mold machine, back-side lithography, and oxide deposition tools, to list a few.
As with any new packaging technology, there will be significant reliability and manufacturability challenges. With underfills and mold compound materials in a WCSP package, the package moisture sensitivity level (MSL) classification might not be MSL1 any longer. Controlling warpage both at the wafer-level during intermediate process steps and at the final package-level will be critical to preclude SMT issues.
TSV dies inherently have lesser strength, which could translate into die cracking or dielectric cracking and delamination issues. Other potential reliability concerns are TSV oxide liner cracking, separation due to CTE mismatch, micro-bump or interconnect reliability, and RDL layer delamination or trace cracking.
WCSP provides clear advantages for customers seeking reduced costs and faster time to market, but is not without its challenges. Over time, WCSP will continue to evolve and grow in demand. The challenges we face today are being met and laying the path for the next generations of packaging—including integrating technologies and 3D structures that will add even more capabilities to semiconductor products.
David Stepniak received his BSEE from Case Western Reserve U. and an MBA from Butler U., and is manager of WCSP and 3D packaging at Texas Instruments, Dallas support bldg., TI Blvd., Dallas, TX 75243 MS 3221; 214-567-9252; firstname.lastname@example.org
Craig Beddingfield received his BSME from Mississippi State U., and is a Wireless Terminals Business Unit packaging development manager at Texas Instruments.
Chris Manack received his BSME from the U. of Oklahoma, and is a high performance analog packaging development engineer at Texas Instruments.
Rajiv Dunne received his PhD in mechanical engineering from the Georgia Institute of Technology, an MS in aerospace engineering from Boston U., and a BE in mechanical engineering from the Birla Institute of Technology & Science (BITS), India, and is a packaging development engineer at Texas Instruments.