As the economics of semiconductor production dictate new efficiencies for supporting market needs, the wafer edge region is emerging as a key focus area in process optimization and control. Kalyan Jami, Srini Vedula and Gerry Blumenstock, KLA-Tencor Corp; Jack Chen, Keechan Kim, Yunsang Kim, and Yung Kim, Lam Research Corp.
Easily post a comment below using your Linkedin, Twitter, Google or Facebook account.
Intel Foundries MEMS for Fuel Cell Start-up Nectar
IFTLE 134 SEMI 3D European Summit – Is the Wide IO Driver Dead?
EUV source roadmaps: Physics vs Engineering
Intel details 22nm trigate SoC process at IEDM
IFTLE 128: RTI 3D ASIP Part 1; Lester the Lightbulb update
Questions and answers on FD-SOI
GlobalFoundries takes on Intel with 14nm finFET “eXtreme Mobility” process
Automated Test Creation for Mixed Signal IP using IJTAG
The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embe...
|
Faster Time to Root Cause with Diagnosis-Driven Yield Analysis
This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software...
|
Innovation in Semiconductor Manufacturing Instrumentation
As the semiconductor industry moves toward smaller geometries, manufacturing processes are becoming more complex. In particular, they’re more deman...
|
3D and 2.5D Integration: A Status Report Live EventThis webcast will explore the present status of 2.5 and 3D integration, including TSV formation. |
Article Archive for Solid State Technology.
