Since the early 2000s, many new electronic materials have been explored and incorporated into silicon CMOS transistors for enhancing their device performance and energy-efficiency. This trend will continue and it is expected that more non-silicon materials will be incorporated into CMOS transistors and integrated onto the silicon substrate in future technology nodes. This article presents results using non-silicon materials to replace silicon as the future transistor channel material and their integration onto silicon.
Since the early 2000s, silicon manufacturers have been exploring many new electronic materials and incorporating them into silicon CMOS transistors to boost their device performance and enhance their energy efficiency. For instance, since the 90nm technology node, silicon germanium has been used to replace silicon to form the source and drain regions of the pMOS transistor to induce uni-axial compressive strain in the silicon channel, thereby increasing hole mobility and improving device performance .
In Intel’s current 45nm technology node, which started volume production in 2007, hafnium-based high-k gate dielectric and dual band-edge work-function metal gate electrodes are used to replace SiO2/polysilicon as the gate stacks of CMOS transistors to increase device performance while significantly reducing gate leakage . Going forward, it is expected that this trend of incorporating more new materials into CMOS transistors will continue and that more non-silicon materials will be integrated onto the silicon substrate in future technology nodes.
Recently, there has been much interest generated and good progress made in the research of non-silicon materials to replace silicon as the future transistor channel material. Among the materials studied are Ge , low band-gap III-V compound semiconductors [4-7], carbon nanotubes , graphene , and so on. These materials, in general, have significantly higher intrinsic (p or n) mobility compared to silicon; thus they have the potential for enabling future high-speed transistors for digital applications at very low supply voltages. Of all these non-Si materials, Ge and III-V compound semiconductors are the most studied, with the latter having been used in commercial communication and optoelectronic products for a long time.
Figure 1. Normalized transistor energy-delay product of n-channel InSb and InGaAs quantum-well field effect transistors (QWFETs) compared to that of standard silicon MOSFETs.
Among the III-V systems of interest, the InSb quantum well has the highest electron mobility of 20,000-30,000 cm2V-1s-1 at sheet carrier density of 1.3 × 1012 cm-2, while an InGaAs quantum well has an electron mobility of 10,000 cm2V-1s-1 at a sheet carrier density of 3.5 × 1012 cm-2. Both InSb and InGaAs quantum-well field effect transistors (QWFETs) show significantly improved transistor energy-delay product, which represents the energy efficiency of the transistor, over standard silicon n-channel MOSFETs, as shown in Fig. 1 .
For III-V compound semiconductors to become applicable for future high-speed and low-power digital applications, they will need to be integrated onto large silicon wafers. A seamless, robust heterogeneous integration scheme of III-V on silicon will allow high-speed, low-voltage III-V based transistors to couple with the mainstream Si CMOS platform, while avoiding the need for developing large diameter (=300mm) III-V substrates.
Besides transistor applications, successful integration of III-V materials on silicon can open up opportunities for integrating new functionalities and features on silicon, such as integrating logic, optoelectronic, and communication platforms on the same silicon wafer. However, heterogeneous integration of III-V on silicon imposes many significant technical challenges because of the large lattice mismatch between the two materials.
Figure 2. Heterogeneous integration of the In0.7Ga0.3As quantum-well (QW) device channel layer on Si using a metamorphic composite buffer architecture consisting of GaAs and InxAl1-xAs graded buffer layers.
A metamorphic composite buffer layer with graded III-V compositions, such as the one shown in Fig. 2 , will need to be inserted between the silicon substrate and the final III-V quantum-well device layer as an effective filter for containing defects without degrading the quantum-well device properties such as carrier mobility. The roles of this composite buffer include minimizing anti-phase domains, bridging the lattice constants, relaxing strain energy and gliding dislocations, eliminating parallel conduction, providing large conduction band-edge discontinuity, and inducing strain to the quantum-well device layer. It also needs to be sufficiently thin for cost reduction and ease of integration with Si CMOS transistors on the same silicon wafer.
Recently, In0.7Ga0.3As quantum-well device structures have been successfully integrated onto silicon using the above composite metamorphic buffer architecture with total buffer thickness scaled down to 1.3µm, as shown in Fig. 3, resulting in high-performance 80nm enhancement-mode In0.7Ga0.3As QWFETs on silicon . The TEM pictures in Fig. 3 show that the misfit and threading dislocations due to the mismatch in lattice constants of the materials are predominantly contained within the composite buffer, and that the active device layers are virtually defect-free. In this research the total composite buffer layer thickness was scaled from >3.0µm to 1.3µm without degrading carrier mobility, as shown in Fig. 4, despite the large (>8%) lattice mismatch between Si and the In0.7Ga0.3As quantum well. This result suggests that the composite buffer is acting as an effective filter for dislocations and maintaining the device properties of the quantum-well layer.
Figure 5. Quantitative mobility spectrum analysis (QMSA) of the In0.7Ga0.3As QW structure on Si at different temperature indicating no parallel, parasitic conduction to the active In0.7Ga0.3As device channel.
Furthermore, quantitative mobility spectrum analysis (QMSA) of this heterogeneously integrated III-V system on silicon shows the absence of parasitic, parallel conduction to the active device channel, as shown in Fig. 5. Compared to the silicon n-channel MOSFET reference, the 80nm enhancement-mode In0.7Ga0.3As QWFET on Si exhibits more than a 10× reduction in DC power dissipation for the same speed performance, or more than a 2× gain in speed performance for the same power, as shown in Fig. 6.
Although III-V QWFETs have shown some very attractive and tangible merits, many technical challenges need to be overcome before the QWFETs will become practical for future high-speed and low-power digital applications. For instance, due to the lack of a stable gate dielectric, currently all of these quantum-well devices use a direct Schottky metal gate, which results in a large parasitic gate leakage. A gate dielectric stack that is compatible with III-V materials will be needed to solve this problem. Also, the formation of an unpinned dielectric/semiconductor interface has been particularly challenging for III-V materials and it is critical toward achieving III-V devices with correct transistor threshold voltages.
Another challenge is the low hole mobility in III-V materials and the lack of a viable p-channel device strategy for the CMOS configuration, which is required for low-power applications. One proposed solution involves improving hole mobility in III-V by incorporating bi-axial strain  and/or uni-axial strain in the device quantum-well channel. Another alternative is to explore the use of other materials with high hole mobility, such as Ge quantum-well systems , for the p-channel transistor. Yet another challenge is the scalability of III-V devices. Like silicon CMOS transistors, the III-V transistor may also need a non-planar structure, such as the Tri-gate transistor structure, to improve its electrostatics with scaling .
Although we are not close to solving all of these technical issues, various research groups in industry and academia have made good progress in tackling these challenges. The recent demonstration of high-performance and low-power enhancement-mode In0.7Ga0.3As quantum-well transistor on silicon substrate via a thin composite metamorphic buffer layer has generated much interest in the silicon and compound semiconductor worlds. Furthermore, if it becomes practical, III-V on Si will be useful for future transistor applications and has the potential to open up new opportunities of integrating new features and functionalities onto silicon. Going forward, research on III-V based transistors and their integration on large silicon wafers will be more exciting and rewarding than ever.
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Robert Chau received his BS, MS, and PhD in electrical engineering from Ohio State U., Columbus, OH. He is director of transistor research and nanotechnology at Intel Corp., 5200 N.E. Elam Young Parkway, Hillsboro, OR, USA; e-mail email@example.com.