In 2003, NXP CAEN opened a new pilot line dedicated to innovative solutions in system-in-a-package (SIP) on 150mm wafers. For metallization, the challenge was to enable the front- and backside metallization on silicon wafers thinned to 200µm without expensive modifications to the existing standard wafer processing equipment. Handling and processing of thin, fragile silicon wafers was demonstrated on a four-chamber MRC Eclipse Mark II sputtering system using a mobile electrostatic chuck technology [1, 2] by ProTec Process Systems GmbH. No modification to the Eclipse system was necessary to enable thin wafer handling.
When Philips (now NXP) looked for possible solutions to its handling requirements, it quickly became obvious that there was no economically feasible way to upgrade the 1980s vintage frontend robot of the Eclipse tool to handle these fragile substrates reliably. However, the ProTec transfer-electrostatic chuck (T-ESC)technology seemed to be an ideal solution to this challenge: enable thin wafer handling on and between existing processing tools without expensive and un-proven modifications to the equipment. To assess the suitability of the new chuck technology, NXP partnered with ProTec.
Description of the equipment used
The Eclipse is an ultra high vacuum sputtering system, widely used in the industry as a production workhorse. From the atmospheric front end, the wafer is inserted into a wafer holder, held by a 1.5mm edge exclusion clamp ring, and passed serially through four vacuum-isolated process chambers. In each chamber, argon gas pressure is built up behind the wafer to couple it thermally to a heated backplane.
The technology is based on the reversible clamping of thin wafers onto a wafer-sized, mobile T-ESC. The bond of thin wafer and the chuck forms a single unit and can be handled by processing equipment and wafer carriers just like a standard thickness wafer. Often the diameter of the chuck is a little bigger to achieve an edge protection for the transferred wafer.
Evaluation procedures and results
The Eclipse PVD system was re-configured for the required titanium (Ti), copper (Cu), and nickel (Ni) deposition cathodes. Initial handling tests inside the deposition chambers were done with ceramic T-ESCs. A central hole in the chuck itself allowed for both efficient pumping out of air trapped between the thin wafer and the chuck, and a sufficient temperature coupling of the thin wafer to the heaters in the deposition chambers, using backside argon gas. The very first 200µm thin handling dummy wafers used were victims of prior misprocessing and had thousands of tiny holes etched all the way through them. They made excellent “worst case” examples for substrate fragility. There was no significant outgasing influence of the T-ESC’s titanium deposition.
Particle measurements that were carried out with a KLA-Tencor Surfscan 4500 system showed that the electrostatic charge of the chuck could pick up contamination generated by the operator of the semi-automated handling tool. Optimizing the interior mechanics of the PROTEC(TOR)-Table and placing the unit in a standard laminar air flow diminishes particle generation during the evaluations significantly. In this way, the number of particles added to the 6-in. product wafers by the electrostatic clamping process could be reduced to <10 with size <0.3µm.
During the evaluations, the ceramic versions of the special chuck were superseded by the high-temperature versions with respect to improved clamping force, very low particle contamination, compatibility with standard in-line wafer cleaning technologies, and compatibility with future high temperature (>400°C) processes.
No significant process shifts for the metal deposition (e.g., influence on deposition rates, uniformity, and crystallization of the films) were detected. The influence of humidity on the current leakage rate of the T-ESC was measured, too and optimized storage protocols and charging profiles made reliable operation possible in environments with relative humidity values up to 50%.
The handling solution mustn’t change the properties of thin films. We have verified that the presence of T-ESC on the wafer’s backside hasn’t changed the heat transfer between the heater of the Eclipse Mark II and the surface of the silicon wafer. Hence, the wafers using the chuck should have the same uniformity, deposition rate, resistivity, and grain size as wafers that were processed without the chuck.
Figure 1. Wafer uniformity (Ti) processing with and without T-ESC.
First, we were interested in the analysis of the difference between a layer of titanium (60nm) deposited at 50°C with or without T-ESC. At this temperature, the deposition rate (around 2.7nm/s) and the uniformity (around 2%) aren’t impacted by the presence of the chuck (Fig. 1).
Figure 2. Copper grain sizes processed with and without the chuck at different temperatures (from 250°C to 50°C).
The second experiment was carried out on copper layer with different temperatures (from 50°C to 200°C) and the sizes of grains were compared with optical MEB observation (Fig. 2).
Figure 3. Wafer uniformity (nm) processing with and without the chuck.
At 100°C the copper grain sizes indicated a difference of morphology. We verified, at this temperature, the uniformity, resistivity and deposition rate (550nm) with or without the chuck. As can be seen in Fig. 3, the uniformity is the same (~2%) and the average of deposition rate is around 11.4nm/s in both cases. Additionally, for nickel deposition, no significant process shifts were observed. The measurement of the capacity of the processed semiconductors and the electrical yield showed additionally no influence regarding the handling with the chuck.
NXP and ProTec have jointly demonstrated that the T-ESC technology is an efficient and straightforward way to enable the processing of 200µm thin, fragile wafers on existing process equipment. No modifications to the equipment were necessary, and its useful lifetime was extended to future product generations. No shift in the properties of the evaluated PVD films has been observed and no defect or electrical charging impact on device yield has been observed. The technology is not limited by wafer thickness, and has been demonstrated down to <50µm by other end users.
The authors thank the staff at NXP and by name, Klaus Beschorner from Metron Technology, for the technical support during the evaluation. T-ESC, Transfer-ESC, Transfer-ESC Technology, PROTEC(TOR)-Table, PROTEC(TOR)-Racket are registered trademarks of ProTec Process Systems GmbH.
- Additional information can be found at www.protec-process-systems.de.
- K.-H. Busse, M. Hinn, “Transfer-ESC Technology for Thin Wafer Production,” Proc. of the 7th International Workshop on Thin Semiconductor Devices, Munich, Nov. 2006.
Philippe Le Duc received his engineer diploma in material science from ENSICAEN Ecole Nationale Supérieure de CAEN and his PhD in material technology from the U. of Lille, France. He is in charge of the Thin Films Group at NXP ICCN, 2 rue de la Girafe, BP5120, 14079, Caen, France; ph 33/2314-52329, e-mail firstname.lastname@example.org.
Karl-Hermann Busse received his degrees in civil engineering from U. of Duisburg and in material science from Technical U. of Berlin, and his PhD in material technology from the U. of Dortmund. He is responsible for R&D programs at ProTec Process Systems GmbH, Birlenbacher Straße 19, 57078 Siegen, Germany; ph 49/0-271 890410, e-mail email@example.com.
Michael Hinn received his degree in electronics from the U. of Siegen. In 2001, he began working on electrostatic handling tools at ProTec Process Systems GmbH.