Nanoimprint lithography provides sub-5nm patterning resolution and may replace photolithography in semiconductor device manufacturing. Nanoimprint has made excellent progress towards implementation as a lithography method for critical device layers, but much work remains in the areas of tool throughput, defectivity, and mold (template) fabrication (analogous to photolithography’s photomask).
Each nanoimprint process creates an inverse replica of the template on the substrate. If a template has more than one level of topography, then a single imprint step generates multiple, distinct levels. There is no specific limit to the number of levels that might be simultaneously imprinted, although template fabrication tends to become more difficult with each additional level.
Since 2004, we have been developing multilevel nanoimprint lithography, in the form of S-FIL, for the specific purpose of process step reductions and simplification in semiconductor device manufacturing. By using multilevel S-FIL, it is possible to eliminate many lithography steps from the overall fabrication scheme. In this way, the unique capabilities of S-FIL are exploited, not because the process can produce smaller features than can be achieved by any optical patterning technology, but because S-FIL offers a lower cost route to manufacturing a structure than can be achieved by any optical lithography process.
In modern integrated circuit (IC) fabrication, copper interconnects provide electrical connectivity among the transistors and to connect the device to the outside world. These copper interconnects are made with the “dual damascene” process, where the vias (vertical wires) and trenches (horizontal wires) are patterned into a dielectric layer in two lithography steps, then simultaneously filled with copper. The damascene process provides a reduction in the number of metal fill and CMP steps, but it still requires 20 or more process steps per wiring layer. Further, the total number of wiring layers in advanced microprocessors has increased to 10 layers. Hence, hundreds of unit process steps are required to complete the interconnect levels in a modern device.
Using multilevel S-FIL with an appropriate imprint template, both the vias and trenches can be patterned in one imprint lithography step. Also removed from the process flow are steps associated with photolithography, such resist coating/baking and wet development. Complications associated with performing a second photolithography step over the topography generated by a first step are also removed, and there is no need for etch-stop or “hard mask” layers in the dielectric film stack, removing interfaces that can induce defects and reducing the effective dielectric constant of the insulator stack.
Pattern transfer of the multilevel imprint into a low-k CVD dielectric is accomplished with a specialized SIM and a multistep etch process. The SIM strategy leverages existing low-k dielectric materials and standard processes, making it simple to implement in existing process flows. No new materials are incorporated into the final structure. SiOC(H) low-k (k <3) dielectrics -Coral from Novellus and Black Diamond from Applied Materials-were used for SIM etch process development.
Further reduction in the number of process steps for interconnect fabrication can be realized by incorporating a directly patternable dielectric (DPD), which replaces the low-k CVD dielectric in the finished device. Additional etch and deposition processes are avoided by incorporating DPD materials into a multilevel imprint process, which represents additional savings for manufacturers.
Figure 1 shows the process for multilevel pattern generation on an Imprio 55 imprint stepper made by Molecular Imprints Inc. The imprint resist precursor, a low-viscosity, photopolymerizable liquid, was dispensed onto the substrate, and a quartz template was brought into contact with the liquid at room temperature and under low imprint pressure to fill the template patterns. Ultra-violet irradiation was used to polymerize the liquid monomer into a solid film, and the template was removed. The resulting pattern was ready for transfer etching into underlying film stacks. The Imprio 55 is a research-specific imprint stepper capable of producing about one, 8 in. wafer per hour with layer-to-layer overlay alignment resolution of sub-1µm, 1σ. More advanced imprint steppers are available from Molecular Imprints Inc. such as the Imprio 250, which is capable of printing 300mm wafers, has higher throughput, and has sub-10nm, 3σ overlay capability.
Figure 1. The multilevel step and flash imprint lithography (S-FIL) process flow.
The techniques used to generate imprint templates are direct extensions of the processes use to fabricate phase-shifting photomasks. For multilevel templates, the lithographic and etch processing are repeated for each desired tier. Figure 2 shows an AFM image of a two-tiered structure used to form the via-1 and metal-2 layers of an electrical test structure. Each test structure is repeated in the design at several dimensions ranging from 2µm-120nm. The areas between the test structures are filled with “dummy metal tiling” (Fig. 2b) to maintain a constant pattern density for improved CMP uniformity. The multilevel templates for this project were purchased from Toppan Photomasks Inc.
Figure 2. a) AFM image of two-tiered, electrical test structures in an imprint template, and b) optical micrograph of a template showing electrical test-structure arrays, with via and metal levels visible.
The standard S-FIL imprint material uses UV-induced free-radical polymerization of liquid imprint resist components, including acrylate monomers and organic crosslinkers along with an appropriate photo-initiator. After polymerization, the imprint resist has sufficient mechanical properties to maintain free-standing, high resolution structures during and after printing.
The SIM is based on standard imprint resist with a specifically designed additive to aid the pattern transfer of multilevel structures into CVD low-k dielectric films. Etching two levels simultaneously requires careful tuning of the etch selectivity between the SIM and low-k materials. Standard imprint resist has a sufficiently high selectivity under common low-k etch conditions to allow for the pattern transfer of high aspect-ratio structures.
Figure 3. a) Directly patternable dielectric (DPD) material based on POSS and BCB, and b) sacrificial imprint material (SIM) components, which after cross-linking can provide multilevel image transfer.
For a multilevel structure, it is desirable to begin transferring the line level before the via has reached the bottom of the low-k layer. This prevents over-etching of via bottoms, and the corresponding damage to barrier layers and copper wiring structures. SIM can be formulated to etch faster under low-k etch conditions than standard imprint resist by incorporating a silicon-containing acrylic crosslinker known as Si-14 (Fig. 3).
Directly patternable dielectric materials
The standard S-FIL imprint resist can function as an electrical insulator, but lacks the thermal stability and mechanical properties needed in an interconnect dielectric for IC device longevity. DPD materials based on polyhedral oligomeric sil-sesquioxane (POSS) have been developed to meet S-FIL processing requirements as well as semiconductor device ILD requirements. The eight silicon “cage-like” POSS species (Fig. 3) represent the smallest possible repeat unit of a silicon dioxide network similar to the silicon oxide films that have been the IC insulator of choice for many years. The design of POSS materials allows a combination of silicon oxide stability and S-FIL imprint capability.
Many researchers have worked with POSS materials to produce functionalized nanoparticles with a vast array of different chemistries. Most of the functionalized POSS materials are crystalline powders, but some derivatives with bulky substituents exist as liquids at room temperature. Richard Laine at the U. of Michigan demonstrated a series of photosensitive liquid POSS materials based on glycidal polymerizable groups.
Inspired by his work, a series of new POSS-based materials were synthesized with acrylate and benzocyclobutate (BCB) functional groups. BCB is a thermally polymerizable functional group used by Dow Chemical in a low-k dielectric resin called Cyclotene. Cyclotene was shown to cure with low shrinkage through a ring opening type polymerization of BCB, resulting in thermally and mechanically stable crosslinks. Although Cyclotene can not be imprinted, the same BCB functionality can be implemented with other chemistries.
We use an allyl-BCB derivative to functionalize the POSS cage structure and render it susceptible to curing at high temperature with minimal shrinkage. This thermally curable functionality was combined with acrylic photopolymerizable substituents to produce S-FIL processable dielectric materials.
Several SIM formulations with different ratios of Si-14 to isobornyl acrylate were made, and their etch rates were characterized. A low SIM etch rate resulted in the via breaching the bottom of the ILD film before the trench bottom reached the ILD surface. Too high of a SIM etch rate resulted in a loss of aspect ratio during pattern transfer. The SIM formulation etch rate was tunable from 22Å/sec to 114Å/sec by loading the SIM with Si-14 from 0 to 97.5%. The standard Coral etch rate was about 40Å/sec; therefore, the SIM was loaded with a low concentration of Si-14 to achieve the desired pattern transfer.
Figure 4 shows cross-section SEMs of imprinted trench and via structures etched with the standard Sematech-ATDF Coral etch recipe. Once the via transfer was complete (Fig. 4b), a descum etch was used to clear the residual SIM from the bottom of trenches. The Coral etch was used again to transfer the trench structure into the ILD substrate (Fig. 4c). Imprint tests have demonstrated successful patterning and etch transfer of the template’s smallest vias, which are 120nm (Fig. 5).
Figure 5. a) Tilt view SEM of 120nm vias imprinted into SIM and b) a cross-section SEM of 120nm vias transferred into CVD dielectric.
A tremendous amount of process latitude was observed for this multistep etch process. Optimizing the gas mixture provides control of sidewall angle and aspect ratio while suppressing faceting and microtrenching. Once the via and trench were formed in the CVD dielectric, standard processes were used for barrier layer and metal deposition. Physical vapor deposition (PVD) was used to deposit 25nm of tantalum and 130nm of copper. No argon sputter was used prior to PVD. After the seed layer was deposited, 1200nm of copper was electroplated to overfill the imprinted features (Fig. 4d).
DPD materials integration
Progress has been made in the design of DPD materials. New DPD imprint materials must meet a list of requirements-including thermal, mechanical, and electrical properties-before implementation as an interconnect dielectric can be considered. Both S-FIL and semiconductor material property requirements must be considered. The new BCB-POSS materials meet many of these demands. Shrinkage and densification during polymerization is always a concern for imprint lithography; however, the vitrification bake process for these materials results in <5% shrinkage. A thermal stability of 343°C was observed for the BCB-POSS polymer; at this temperature, the dielectric loss is 1 wt% per hour. The IC standard for on-chip interconnect thermal stability is 400°C, so additional work is required to develop either the material or the integration scheme.
The BCB-POSS dielectric constant (2.89) meets the requirement of <3 for low-k interconnects, and incorporation of porogens provides a route to reducing the value. The elastic modulus of a fully cured BCB-POSS was determined by nano-indentation to be 1.89GPa. A modulus of 4GPa or higher is suggested for CMP processing success. However, a low down-force CMP process has already shown some success at the ATDF with acrylic dielectric films possesing a modulus less than 1GPa.
The coefficient of thermal expansion (CTE) of BCB-POSS is 32ppm/°C, which results in a copper/dielectric mismatch of about 15ppm/°C. Ideally there would be no CTE mismatch between the dielectric and the wiring metal, but this mismatch is similar to the mismatch for copper/CVD-TEOS interconnects (16.5ppm/°C). BCB-POSS based materials are poised for introduction to the ATDF copper damascene process for fabrication of electrical test structures.
Multilevel S-FIL streamlines on-chip interconnect fabrication by removing difficult photolithography and photolithography related steps from the dual damascene process. Multilevel S-FIL enables the patterning of two circuit levels in a single step, and reduces the overall number of fabrication process steps by a third to a half depending on whether the imprinted material is a SIM or DPD. Over 100 unit process steps can be removed from the manufacturing of an 8-layer metal interconnect structure.
The SIM is an imprint resist with tunable etch selectivity relative to a CVD low-k dielectric, which can be used to simultaneously transfer trench and via structures into low-k SiOC(H) with tremendous process latitude. Directly-patternable dielectrics (DPD) represent a significant chemistry/materials science challenge relative to the SIM, as all the requirements of an imprint resist and a low-k dielectric must be realized in a single material. Dual-functionalized POSS materials meet nearly all the material properties requirements for S-FIL and dual-damascene processing.
Step and Flash, S-FIL, and Imprio are registered trademarks of Molecular Imprints Inc. Coral is a registered trademark of Novellus Systems Inc. Cyclotene is a registered trademark of Dow Chemical Inc. Black Diamond is a registered trademark of Applied Materials Corp.
Frank Palmieri received his bachelors in chemical engineering from Virginia Commonwealth U. in 2002, and is a graduate research assistant at The U. of Texas at Austin, Chemical Engineering Dept., 1 University Station C0400, Austin, TX 78712; ph 512/471-6364, e-mail email@example.com.
Michael D. Stewart received his bachelors from Vanderbilt U. in chemical engineering and his PhD in chemical engineering at The U. of Texas at Austin while working in the research group of Grant Willson. He now attends law school at The UT-Austin.
Wei-Lun “Kane” Jen is a graduate student in the department of chemical engineering at The U. of Texas at Austin. He received his bachelors in chemical engineering from The UT-Austin in May 2000.
Gerard M. Schmid received his PhD in chemical engineering from The U. of Texas at Austin and is a senior template scientist at Molecular Imprints Inc.
C. Grant Willson received his BS and PhD. in organic chemistry from the U. of California at Berkeley and his MS in organic chemistry from San Diego State U. He came to The U. of Texas in 1993 from his position as an IBM Fellow and manager at the IBM Almaden Research Center. Willson researches the design and synthesis of functional organic materials with an emphasis on materials for microelectronics. For more information please go to http://willson.cm.utexas.edu.