Making reliable systems through direct interconnection between dice requires proper integration of via-processing technology as well as thinning and stacking technologies. All technology variations influence stack performance and cost, and the seemingly most obvious choice for any one technology does not always lead to the best overall system integration.
A primary driver for exploring the third dimension is physical size reduction. A second reason to explore 3D stacking is performance, with short interconnects between chips allowing for higher operating speeds, lower power consumption, and reducing the need for large input/output drivers. A third, and perhaps ultimately more important reason, is the opportunity for hetero-integration of different technologies requiring diverging process flows-such as analog, logic, memory, and MEMS-being finally stacked to build a system. Hetero-integration provides many advantages, particularly with respect to cost, compared to integrating the variety of process flows into a single one.
3D integration may involve stacking of partially packaged systems, subsystems, components, dice, or even wafers. Some of these technologies are already in the market while others have yet to appear. Each has different relative advantages for specific applications, depending on the degree to which the enhanced performance of a stacked system can justify the added complexity and cost of the 3D processes .
Figure 1. Illustration of the 3D-SIC concept where two thin ICs are stacked upon a thicker device.
The 3D-stacked IC (3D-SIC) technology that we have developed enables extremely high through-Si interconnect densities-up to 10,000/mm²-for logic applications or for stacking memory on top of logic. It integrates the through-Si vias (TSV) using a “Cu-nail” production process in the post frontend-of-line (FEOL) foundry process. Figure 1 shows Cu nails with typical diameters between 1 and 5µm at a pitch of 10µm or below.
As we revealed at the 2006 IEDM conference in San Francisco , this process uses single-damascene techniques on bulk Si wafers to form blind Cu vias immediately after the contact layer and before processing the backend-of-line (BEOL) metal layers. In this way, BEOL routing capabilities are left unaffected.
The TSVs are opened at the wafer backside by aggressively thinning the Si-wafer. Singulated dice from the thinned wafer are then attached and electrically interconnected to a Cu/dielectric landing substrate. Electrical connection occurs though a direct Cu-Cu thermo-compression bond or a hybrid bond combining Cu-Cu with dielectric glue. Major differentiators from other advanced 3D approaches are the Cu-via processing before applying BEOL metallization, and the direct Cu-Cu bond that avoids intermetallic formation at the bonded interface.
When optimizing the 3D-SIC processes, overall process integration issues must be managed. Since via processing, wafer thinning, and the bonding process are done after frontend device formation, the thermal budgets of the processes involved must be compatible with the presence of devices on the wafer.
We have demonstrated vias 5µm in dia. and 24µm deep. Optimizing the via etch process obtained straight and smooth sidewalls for large aspect ratios . To electrically isolate the vias from the silicon, an oxide liner was applied inside the etched openings. Oxide deposition was done at 420°C, which is well within the temperature-budget limits imposed by FEOL devices. After isolation, the vias are filled using what is similar to a standard copper single-damascene process. Our demonstration experiment included an additional single damascene Cu/oxide layer on top of the vias to provide top-traces for the chain. After via filling, regular BEOL processing can be resumed.
At this point in fabrication, the Cu vias are still “blind” at the bottom and only penetrate the top layer of the Si wafer. To expose the bottoms for electrical interconnections to a lower level die, we use a three-step thinning process facilitated by a temporary carrier [4, 5]. The wafer with the Cu TSVs is therefore glued onto a nonpatterned Si carrier wafer using a removable glue layer in a wafer-to-wafer bonding process.
Figure 2. SEM picture of a single Cu via protruding from the backside of the wafer after plasma etching.
In the first thinning step, the wafer is ground down to a target thickness slightly greater than the via depth, such that the TSVs remain unexposed. The second step is a two-part chemical-mechanical planarization (CMP) process that removes additional bulk-Si to expose the TSVs and then removes Cu residues from the silicon surface . In the third and final thinning step, the Si is selectively plasma-etched so that the TSV Cu nails protrude ~1µm from the backside of the thinned wafer (Fig. 2).
As a result of this sequence of grinding, CMP, and etching, the oxide liners and barriers at the bottoms of the once-blind TSVs are removed when the Cu inside is exposed. The thinned patterned wafer-at this point less than 20µm thick-and the attached carrier wafer are subsequently diced in a regular blade-dicing process.
In parallel to the TSV process flow, the landing wafer-on top of which the dice containing TSVs will be stacked-can be prepared. In our demonstration experiment, the landing wafer was fabricated using a single damascene Cu/oxide process to form the landing pads for the TSVs as well as the bottom traces of a TSV chain.
The singulated thin-die/carrier stacks were bonded to the landing wafer in a standard flip-chip bonding tool. The thermo-compression bonding process was kept as basic as possible. No soldering with soft bonding metals was applied, allowing for direct contact between the Cu vias and the Cu pads on the landing wafer. In this way, no intermetallic formation has to be taken into account at the contact interface.
However, for successful Cu-Cu bonding, it is imperative that no surface oxidation occurs before or during the bonding process. Since the slightest amounts of copper oxide can result in mechanical and electrical degradation of Cu-Cu bonds, surface treatment of both the TSVs and landing wafer is mandatory. Of the several investigated options, a dip in a dilute citric acid solution achieves the best results when testing the shear strength after bonding ; the Cu-Cu bonded interface displays a lateral shear stress resistance exceeding 20MPa. To ensure compatibility with finished IC devices, the thermo-compression process was executed at a temperature ranging from 300-350°C. Though lower temperatures worked equally well mechanically, they resulted in electrical malfunctions in the via interconnections.
In the last stage of the process, the carrier dice are released from the bonded thin dice in a thermal or chemical process. Finally, glue residues are removed from the topside of the stacked thin dice in a wet or plasma clean process.
Figure 3. a) SEM image of a cross section FIB of one element of a 3D-SIC via chain, and b) detail of the bonded interface between the Cu via and the landing pad.
A cross-section scanning electron microscopy (SEM) inspection revealed that the stand-off between the two dice in the stack is well below 1µm. Also, there was no evidence of Cu-grain growth across the bonded interface (Fig. 3).
Figure 4. SEM image of a 3D-via chain left after the top silicon die was completely etched away.
Besides mechanical and SEM inspection, electrical functionality of the TSVs was demonstrated. Figure 4 shows a section of a 10.6mm × 10.6mm test chip containing two 10,000 TSV chains formed with 5µm diameter and 10µm minimal pitch. These test structures showed that 67% of the chains were fully functional, and shorter fractions of all other fabricated chains were functional. In all cases, ohmic behavior was observed (Fig. 5).
3D-SIC thermal performance
While our demonstration experiment involved stacked dice for which the only physical contact is through the electrical interconnects, in a product application a dielectric will need to be included in between the stacked dice. In addition to providing mechanical stability to the thinned dice in areas with a low number of interconnects, the dielectric glue layer will thermally connect the stacked dice and allow dissipation of heat throughout the different layers.
Figure 5. I-V curve recorded on a 10k 3D-via chain illustrates ohmic behavior.
As the power density of high-performance circuits reaches or even surpasses the classic cooling limits of 100W/cm², thermal management becomes a vital issue. The ITRS roadmap indicates a continuing rise for the maximum power of high-performance processors, and a decrease in the maximum allowable junction temperature. Stacking dice effectively increases the power dissipation per unit area, and low-k intermetal dielectrics are poor thermal conductors, so understanding heat dissipation in stacked systems is a critical success factor to bringing stacking technologies to market.
We have developed a semi-analytical model that can be used to estimate the thermal resistance for any given 3D-SIC geometry . This model can be used for fast network-type simulations of a given stack’s thermal behavior, thus avoiding the need for ‘trial-and-error’ processing and shortening the stack development cycle. Preliminary results indicate that the area from which Cu nails can capture heat in order to quickly evacuate it remains highly localized to an area of two to four times the nail diameter. Only for high Cu-nail densities is a reduction of the overall thermal resistance of the stack observed.
The thickness of the silicon in the stacked dice and the TSV diameters appear to have marginal impact on heat dissipation. The presence of the interfacial dielectric glue layer, typically a weak thermal conductor, does increase the maximum junction temperature, and the thickness of this layer needs to be minimized for optimal thermal performance. For an inter-die dielectric layer thinner than 5µm, however, the thermal resistance of the overall stack is dominated by the contribution of the on-chip Cu/low-k BEOL layers.
Cost of stacking technologies
Our results demonstrate the technical feasibility of the 3D-SIC integration approach. However, it must be cost effective since 3D-SIC, versus mainstream development work, focused on die-to-wafer (D2W) stacking techniques rather than on wafer-to-wafer (W2W) bonding. While throughput considerations generally favor W2W stacking, the use of D2W stacking in combination with known-good-die (KGD) enables optimization of the yield of the stacked systems (Fig. 6). Indeed, the main additional cost of a 3D-stacked system comes from any yield losses due to stacking.
Figure 6. Comparison of D2W versus W2W three layer bonding illustrates the yield benefit of D2W stacking of known-good-die (KGD).
A thorough analysis of the stacking cost reveals that the stacking and bonding process costs are small compared to the cost of lost-good-die (functional die combined with nonfunctional die in a stack). Consequently, W2W bonding schemes can only be used with very high yielding wafers or very small dice. For D2W stacking, true KGD are required. Even a simple die screening IDDQ test can provide ‘good-enough-die’ to dramatically decrease the cost of stacks. In addition to cost consideration, diverging die-sizes also inherently favor D2W stacking; hence it is favorable for a majority of applications.
Now that the feasibility of 3D-SIC integration has clearly been demonstrated, reliability of 3D-SIC stacks will need to be established. Apart from classical reliability testing, we also plan to evaluate the influences of 3D-TSV proximity and extreme wafer thinning on the electrical performance of the stacks.
- E. Beyne, “3D System Integration Technologies,” Symposium on VLSI Technology, Hsinchu, Taiwan, pp. 19, April 2006.
- B. Swinnen et al., “3D Integration by Cu-Cu Thermo-compression Bonding of Extremely Thinned Bulk-Si Die Containing 10µm Pitch Through-Si Vias,” International Electron Devices Meeting: IEDM. Technical Digest, IEEE, San Francisco, CA, United States, Dec. 2006.
- J. Van Aelst et al., “High Aspect Ratio Via Etch Development for Cu Nails in 3-D-stacked ICs,” Dry Process Symposium, Nagoya, Japan, Nov. 2006.
- K. De Munck et al., “Wafer-level Temporary Bonding/debonding for Thin Wafer Handling Applications,” IMAPS International Conference and Exhibition on Device Packaging, Scottsdale, AZ, United States, (CD-ROM proceedings), March 2006.
- K. De Munck, et al., “Grinding and Mixed Silicon Copper CMP of Stacked Patterned Wafers for 3D Integration,” MRS Fall Meeting Symposium Y: Enabling Technologies for 3-D Integration, Boston, MA, United States, Nov. 2006.
- J. Vaes et al., “Mixed Silicon Copper CMP on Stacked Patterned Wafers for 3C Stacked IC Integration,” Proceedings of the International Conference on Planarization/CMP Technology: ICPT, AVS CMP Usergroup, Foster City, CA, United States, (proceedings digitally available) Oct. 2006.
- W. Ruythooren et al., “Direct Cu-Cu Thermo-compression Bonding for 3D Stacked IC Integration,” Proceedings of the International Symposium on Microelectronics, San Diego, CA, United States, Oct. 2006.
- C. Chen et al., “Enabling SPICE-type Modeling of the Thermal Properties of 3D-stacked IC’s,” Proceedings of Electronics Packaging Technology Conference, Singapore, pp. 492-499, Dec. 2006.
Koen Snoeckx received his masters degree in biochemistry in 2001 from the U. of Antwerp, Belgium. He is a scientific editor at IMEC, and is jointly responsible for authoring and editing technical documents and publications. IMEC, Kapeldreef 75; 3001 Leuven, Belgium; ph 32/1628-8245, e-mail Koen.Snoeckx@imec.be.
Eric Beyne received his degree in electrical engineering in 1983 and his PhD in applied sciences in 1990, both from the K.U. Leuven, Belgium. He is program director of the Advanced Packaging and Interconnection Center at IMEC. He is president of the IMAPS-Benelux committee, member of the IMAPS-Europe Liaison committee, and member of the board of governors of the IEEE-CPMT society.
Bart Swinnen received his PhD in solid state physics in 1997 at the K.U. Leuven, Belgium. He is a program manager at IMEC, first starting in 2003 with the wafer-level packaging program and later for the 3D-SIC program. Before joining IMEC, he worked for three years as a developer at ASML.