Traditionally, semiconductor manufacturers have used two main methods to increase fab productivity. The first has been to implement changes such as continued device scaling and the move toward larger wafer sizes. The second method has been to rely on incremental technological improvements in tool capability. However, as scaling becomes more difficult and the cost of 300mm fabs escalates, manufacturers must put a similar effort into identifying and addressing the impact of even routine impediments to fab productivity and, particularly, the impact these have on cycle time. One technique is to use a comprehensive fab simulation model to determine the impact of such factors as wafer success rate improvements.
One of the main contributors to cycle time is the impact of tool-measurement interrupts due to nonoptimal recipe creation. Some semiconductor manufacturers have started to address this opportunity and have realized productivity benefits. IBM , for example, has improved its fab productivity by improving recipe quality on one of its metrology tool sets. Through a process of identifying and optimizing the recipes that decreased productivity, IBM ultimately improved capacity approximately equivalent to one tool, thereby increasing availability and decreasing cycle time at that tool set.
One challenge facing the industry is to be able to quantify the impact of recipe optimization in terms of availability, utilization, cycle time, and productivity at the tool, fleet, and fab levels. The first step in addressing this challenge is to define a standard metric for measuring interrupts. One solution is to use a metric such as the wafer success ratio (WSR), which is the percentage of wafers that run without an interrupt divided by the total number of wafers run through the tool, that is, WSR = (successful wafers) / (total wafers). The WSR metric can provide a baseline of tool and fleet productivity and to measure progress in recipe and tool performance over time. An investigation into typical wafer success metrics at leading fabs indicates an opportunity to improve tool productivity by up to 15%.
Fab simulation model
At the fab-wide level, it is more challenging to see the impact of wafer success improvements because multiple events occur simultaneously, making it difficult to isolate the real driver of the overall cycle time improvement. A possible solution is the development of a fab simulation model where extraneous factors can be controlled, thus showing how wafer success improvements can influence higher-level fab metrics, such as total production and cycle time.
The results presented in this paper were generated from a comprehensive state model that simulates the flow of wafers through a fab. The model can simultaneously simulate up to four different process flows, each with up to 800 steps in a fab with 80 toolsets and up to 20 tools in each set. The model works by statistically assigning states to each of the lots (e.g., on hold, in queue, being processed, etc.) and to each of the tools (e.g., up, down, busy, idle, etc.). A simulation clock moves in two-minute intervals, and the program updates the state of every tool and every lot in the fab and moves the lots through the fab in accordance with a fab-specific, customizable process flow (or run card).
The run card contains all of the information about how to process the lot at each step-the toolset used, number of wafers processed, and, where applicable, the target, distribution, and specification limits for film thickness, CDs, overlay, and defects-thus making the model customizable to any fab environment. Each process step can assign up to three different parameters to the lot. For example, a lot going through a photo step could be assigned values for CD, overlay, and defects, each of which could then be “measured” at a subsequent measurement step.
The tool data is handled separately and each toolset can be assigned a host of productivity and reliability characteristics including throughput, mean time between failure (MTBF), mean time to repair (MTTR), qual period, qual time, preventive maintenance (PM) period, PM time, precision, and matching. Additionally, the model can simulate two different cases of wafer success interrupts: one in which some manual intervention is required but the lot does not have to be removed from the tool, and a second in which the lot has to be put on hold. In both cases, one can specify the mean time between assists (MTBA), mean time to assist (MTTA), and the average lot-hold time (where applicable).
The figure shows the impact on cycle time as a function of the WSR on overlay tools in a fab with 20,000 WSpM for overlay tool utilization rates of 60%, 70%, and 80%. Each of the three curves is normalized to a cycle time of 50 days at 100% WSR. The simulations were done for a nine-metal level process with 29 photo steps and 29 overlay measurements. Skipping measurements was not allowed. The MTTA of a failed recipe was five minutes, and half of the failures were programmed to result in the lot being put on hold for an average of 30 min/incident. The utilization of the overlay tools was adjusted by changing the average number of wafers measured at each step which, in the simulation, only affects the processing time and has no effect on WSR. Each data point represents the average of 10 years of simulated production.
Clearly and expectedly, the impact of WSR is much greater at higher tool utilizations, but even at 60% utilization, the difference between 80% WSR and 100% WSR corresponds to a 1.25 day reduction in cycle time (1.5 hours of cycle time/% WSR).
The increase in cycle time comes from two sources, the obvious contribution being a lot idling for five minutes waiting for the operator to assist the failed recipe. However, even at a WSR as low as 80%, this only adds ~29 min of cycle time to each lot (29 measurement steps each with a 20% chance of needing assistance at 5 min/assist).
The real issue is lost availability. At 9600 lots/year (20,000 WSpM) there will be 55,680 assists, or 4640 hours of lost availability. Spread over three overlay tools, this amounts to 1547 hours (17.7%) of lost availability per tool per year. This is why the WSR has such a huge impact at higher utilizations.
To a semiconductor manufacturer looking to optimize cycle time, this model shows the financial benefits of improving fab productivity by focusing effort on monitoring and optimizing recipe performance.
By using a comprehensive state model to simulate wafer fab production, one can isolate and measure the financial impact of operational issues such as wafer success. As shown by the fab simulation model, the impact of wafer success improvements will be measured in millions or even tens of millions of dollars depending on the utilization of the tool set in question and the severity of the WSR problem. However, to capitalize on this opportunity, it is imperative that the semiconductor industry put effort into developing efficient ways to manage the process of optimizing wafer success interrupts.
Manual optimization methods are unrealistic as the number of recipes grows and the fab environment becomes more complex. Automated methods must be developed to extract tool interrupt information, generate and plot summary performance metrics, perform drill-down analysis, identify root cause, and provide and store results and plans of action.
- E. Solecky, “Emerging Lithographic Technologies X,” ed. by M. Lercel, Proc. of the SPIE, Vol. 6152, pp. 288-303, 2006.
Doug Sutherland received his PhD in chemical physics from the U. of Western Ontario. He is the senior manager of technical marketing for KLA-Tencor’s Global Support Services Division, 160 Rio Robles Dr., San Jose, CA, 95134; ph 408/875-9638, e-mail Doug.Sutherland@KLA-Tencor.com.
Marc Wilkinson received his BSc in mechanical engineering from Queen’s U., Canada, and his MBA from the Stephen M. Ross School of Business at the U. of Michigan. He is product marketing manager for KLA-Tencor’s Global Support Services Division.
Doug Sutherland, Marc Wilkinson, KLA-Tencor Corp., San Jose, California