The ability to improve IC manufacturing costs has been one of the great success stories of the semiconductor industry. The dramatic reduction in cost per transistor has been enabled by vast technology innovation. Recent data indicates that the semiconductor industry is poised to depart from the historic rate of productivity improvement . One potential way to improve productivity is to reduce fab cycle time. With these challenges in mind, International Sematech Manufacturing Initiative (ISMI) began its 300mm Prime initiative to address fab productivity challenges going forward and ensure that the industry does not fall behind its historic rate of improvement .
Among the most pressing productivity challenges in IC manufacturing is process “waiting time.” For every one minute that a wafer is being processed inside a tool, that wafer may spend 20-30 minutes or more unproductively “waiting” for the next part of the fabrication process to begin. Cycle-time reduction affords IC manufacturers the opportunity to optimize fab logistics significantly, reducing unproductive time and improving overall fab productivity. Reducing the wafer lot size within a carrier can most directly cut cycle time. In doing so, fab automation must be advanced to support higher carrier move rates and the resulting higher reliability required. It is envisioned that this factory logistic solution can be implemented in the next 3-5 years prior to the migration to a larger wafer size, which may be advantageous for early adopters. Moreover, the resulting development and demonstration of the solution can reduce risk for the entire industry. These are the challenges that 300mm Prime is expected to address.
For years, semiconductor fabs have been seeking ways to improve their manufacturing productivity. Various attempts and methodologies, most of them based on process equipment innovation (rather than on manufacturing innovation), have been implemented. For example, semiconductor manufacturers have switched to larger wafer sizes, yielding more die per wafer, to enhance fab productivity. Moreover, ongoing investments in process equipment have enabled die shrinks, yielding still more die per wafer. Though both of these innovations have dramatically reduced cost-per-die, there are other ways to increase productivity.
Learning from the past: “200mm Prime”
In the late 1980s, process equipment suppliers transitioned to 200mm wafers and process tools capable of loading automatically from open wafer cassettes. In the early 1990s, some IC manufacturers concluded that eliminating the manual handling of wafer cassettes could reduce the introduction of undesired particles into the chipmaking process, enabling further productivity gains . Consequently, they developed and adopted standard mechanical interface (SMIF), a standardized “isolated carrier” methodology for transporting wafers between process equipment.
Unlike past attempts at fab productivity enhancement, which had focused on process equipment, SMIF was manufacturing-oriented; it provided a productivity enhancement with minimal to no impact on process tool architecture, sharing the productivity enhancement burden between process tool and automation suppliers. SMIF enabled both improved die yield and wafer-handling or “factory” automation approaches that had not been previously possible in an exposed wafer environment. SMIF gave IC manufacturers who adopted it a clear competitive advantage.
As IC manufacturers recognized the productivity improvements of SMIF, it became increasingly adopted in 200mm fabs. Later, when 300mm wafers were introduced, IC manufacturers realized that there was little risk in adopting the now-proven “closed-container” SMIF approach. The SMIF equivalent for 300mm manufacturing, the front-opening unified pod (FOUP), was adopted by all IC manufacturers at the 300mm wafer size transition.
Looking back, we suggest that the adoption of SMIF represented a first derivative of 200mm manufacturing methodology or the “200mm-Prime” generation of IC manufacturing.
Looking to the future: 300mm Prime
Enhancing manufacturing productivity in fabs today continues to be one of the most important challenges facing IC manufacturers. As noted previously, a key opportunity to improve productivity is to reduce cycle-time latency caused when wafers-in-process wait to get through each process step.
The loss of revenue and profit caused by waiting wafers takes many forms, some of which include: 1) the inability to meet demand due to extended ramp and production cycle times; 2) the incremental expenses related to extended ramp and production cycle times; 3) the opportunity cost due to lengthy cycles of learning; and 4) the erosion of return-on-assets because of excessive work-in-process (WIP). In each of these examples, reducing cycle times can and will reduce the unit cost per wafer and improve responsiveness to customer demand.
Studies by Prof. Robert Leachman at the U. of California-Berkeley, Samsung Electronics, and others have already demonstrated that cycle-time reductions can significantly improve productivity, reducing cost-per-wafer, which is part and parcel of the primary argument for 300mm Prime . Leachman also noted that the cost of delay in manufacturing IC chips can rival the steady-state manufacturing cost of a wafer .
Reducing unproductive idle time
Wafer carriers in fabs today carry as many as 25 wafers. At each step, the carrier must wait while each wafer is processed. Consider what can happen if the number of transported wafers is reduced to five. Once the five wafers have been processed, the carrier quickly moves onto the next process step. As a result of this simple-sounding change, “dead” time drops and cycle time improves dramatically. The overall amount of WIP in the plant drops, improving return-on-assets (ROA) (Fig. 1). A reduction in transported lot size enables IC manufacturers to reduce cycle times by significantly reducing unproductive idle time.
Figure 1. Normalized WIP/cycle time vs. wafers/carrier.
The productivity benefits of reduced cycle time are wholly consistent with the intent of the 300mm Prime productivity improvement initiative. But what exactly does this mean to everyone in the semiconductor industry-from IC manufacturers to process equipment suppliers and automation suppliers? Let’s look at each:
IC manufacturers. Although faster cycle times may be a key benefit that IC manufacturers can realize from 300mm Prime, it also significantly enhances their ability to design and deploy (or upgrade to) more responsive fabs capable of processing a far more diverse mix of products more quickly, all of which points to improved asset utilization and greater return on investment (ROI). Additionally, because 300mm Prime enables manufacturing flexibility-diverse chips can be manufactured more readily in a single 300mm Prime fab-IC manufacturers stand to benefit substantially from the ability to turn around orders quickly and inexpensively. It is expected that 300mm Prime will be developed to enable variable lot and carrier sizes according to the needs of the IC manufacturer.
Other benefits IC manufacturers will realize include: 1) recapture of lost revenue from the elimination of lengthy ramp and production cycle times; 2) reduced amortized expense for lengthy ramp time; 3) reduced opportunity cost for lengthy cycles of learning; 3) improved ROA from reduced WIP; and 4) improved customer responsiveness and time-to-money.
Process equipment suppliers. Process equipment suppliers benefit from the fact that factory automation vendors will now share more of the productivity improvement burden with them. We suggest that 300mm Prime factory automation changes should be bounded at the SEMI E63-1104 Box Opener/Loader to Tool Standard (BOLTS-M) interface-the standard interface by which loadports are mounted to process equipment-enabling the process equipment interface itself to remain principally unchanged. We also suggest that advances in 300mm Prime carriers and loadports will simplify process equipment and aid the next wafer-size transition.
Automation suppliers. Automation suppliers can differentiate their products by developing high-value logistics solutions. Historically, advances in factory automation have been essentially evolutionary, from the need to store lots in stockers, to the recent ergonomic need to transport FOUPs because of their weight. Additionally, factory automation has been principally designed by committee and by standards-setting organizations. Currently under consideration is whether future factory logistics will become more of a differentiator for IC manufacturers, especially as the number of IC manufacturers tends to decrease as wafer sizes increase.
Challenges facing 300mm Prime implementation
If 300mm Prime is going to be commonly adopted, there will be a need for some automation interface standards to be developed, for example, carrier or loadport standards. A challenge will be to develop these standards without stifling significant logistics improvements. There are also real challenges simply due to the increased number of carrier moves within a fab.
IC manufacturers, in an effort to reduce cycle times with current automation, run fewer than 25 wafers in carriers built to accommodate 25. Cycle time improves, but clearly, achieving the full benefits of reduced lot size requires the use of automation solutions designed to maximize, dependably and safely, the movement rate of small lots.
Reducing lot sizes from 25 wafers/pod to five wafers/pod means moving the same number of wafers through the factory with five times more “moves” (inversely proportional observation). This increase in the number of moves challenges automation manufacturers since they must build equipment that can both support these move rates and prove more reliable. The number of carriers does not increase by 5× because the fab simulation modeling we have performed has significantly reduced WIP. The need for higher move rate lot deliveries will likely necessitate approaches that position WIP closer to the process equipment, a.k.a. distributed WIP, as opposed to remote storage in stockers (Fig. 2).
Figure 2. Normalized number of carriers vs. wafers/carrier; and normalized number of AMHS moves/hr vs. wafers/carrier.
Additionally, because FOUP and SMIF are aging, there is an opportunity to make the wafer-handling environment cleaner with 300mm Prime. Specifically, automation suppliers must consider both tighter molecular contamination control and gas species exposure control not only for 300mm Prime itself, but also with an eye toward larger wafer size manufacturing.
A final challenge of note is that new metrics may be required within the International Technology Roadmap for Semiconductors (ITRS) to better enable driving cycle-time reduction roadmaps. For example, the ITRS currently uses a cycle-time metric “X-factor” corresponding to total cycle time divided by raw process time. Since the raw process time includes the total time the carrier spends at each tool, X-factor provides no insight into the non-value added time spent at the tool.
Figure 3. Normalized X/Y factor vs. wafers/carrier.
New cycle-time metrics are needed to better capture this opportunity. Such a metric may be a “Y-factor” corresponding to the total cycle time divided by minimum process time at the wafer level. Here, the minimum process time would include value-added steps only, such as objective process steps (e.g., per SEMI E79-0304) and absolutely necessary supporting steps (such as heating, cooling, pump/vent, required alignment). By contrast, the current X-factor ITRS  reflects cycle-time improvements only relating to AMHS transport at a lot level; however, a new Y-factor roadmap would reflect cycle-time improvements in the overall factory, necessitating improvements such as reduced capacity carriers and supporting high move rate transport systems. Here, Y-factor represents a more direct ratio of overall cycle time relative to the time that process-related value is actually being added to the wafer (Fig. 3).
Recent data indicates that the semiconductor industry is posed to depart from the historic rate of productivity improvement . Although process equipment-innovation-based efforts have succeeded in the past, it is becoming clear that a more fundamental change may be necessary, one without significant implementation costs but with compelling benefits. Cycle-time reduction poses a potential solution. From an automation perspective, further innovation is required since higher move rates are needed to achieve the desired level of cycle-time improvement and resulting productivity.
Productivity improvements achieved with 300mm Prime should provide a scalable bridge to the next wafer size with significantly lower transition risks. As with 200mm Prime, early adopters may realize a competitive advantage. History was made with 200mmPrime, and 300mm Prime just may be history repeating itself
1. Denis Fandel, ISMI Global Economic Symposium, Capacity and Productivity Trends presentation, January 25, 2006,
2. Go to http://ismi.sematech.org
3. Stuart A. Hoenig, PE, PhD, “Why Our Fab is a SMIF Facility,” A2C2 Magazine, July/August 2000.
4. Robert C. Leachman, Jeenyoung Kang, Vincent Lin, “SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics,” INFORMS Journal Interfaces 32:1, pp. 61-77, 2002.
5. Robert C. Leachman, John Plummer, Nancy Sato-Misawa, Understanding Fab Economics, Report CSM-47, Competitive Semiconductor Manufacturing Program, U. of California at Berkeley, June 24, 1999 (see http://esrc.berkeley.edu/csm/csmab.html for Leachman’s 1999 study).
6. http://public.itrs.net. All references to the ITRS are from the 2005 version.
William Fosnight received his BSME from Ohio State U. and his MSME from Rensselaer Polytechnic Institute, and is named inventor on some 25 patents. He is senior VP, engineering, at Brooks Automation, 15 Elizabeth Drive, Chelmsford, MA 01824; ph 978/262-2601, e-mail firstname.lastname@example.org.
Christopher Hofmeister received his BS degree in mechanical engineering from Pennsylvania State U., his MS in engineering, control systems, and signal processing from Northeastern U., and his Juris Doctor from the Massachusetts School of Law. He is named inventor on over 25 patents and is senior VP, Advanced Technology Development, and CTO of the Semiconductor Products Group at Brooks Automation.