OPC models for leading-edge lithography must be calibrated with empirical data, and the measure of mismatch between design-intent and CD-SEM data is termed edge-placement error (EPE). A new methodology of EPE measurement uses an automated CD-SEM as part of an OPC model building and process qualification flow. Design-based classification of edges and EPE defines many orientations such as line-end-adjacent, line-end, corner, and other critical gate edges. Also, the CD-SEM edge contours can be converted into an OASIS file for the construction of a process variability band (PVband) to quantify variability for all two-dimensional (2D) contexts.
Optical proximity correction (OPC) plays a vital role in the lithography process of cutting-edge IC fabrication. The quality of lithography models used in OPC is fundamental to the final performance of the OPC in production. Traditionally, 2D proximity features such as line-end, bar-to-bar, or bar-to-line were only partially characterized because of the difficulty in transferring the SEM information into the OPC model building process.
It is not easy to generate EPE measurements because of the inherent need to overlay the design and the SEM in order to quantify EPE. The quality of the EPE measurement depends not only on the accuracy of the SEM image scan rotation and magnification, but also on the accuracy of matching between the design layout pattern and the realized pattern (wafer). These problems do not exist in simulation, but model calibration requires a direct comparison between simulation and measurement. Measuring EPE effectively brings the measurement information into the realm of the design.
CD-SEM automation, including setup of the CD-SEM recipe and CD-SEM image acquisition, is no longer the constraint in OPC model calibration and process/product qualification [1, 2]. CD-SEM recipe refinement, to create results which can be correctly interpreted, is the key to successful use of the CD-SEM. Historically, a one-dimensional (1D) measurement was made on a 2D feature, and the result was used in model building and qualification. A new method of EPE measurement using CD-SEM is proposed as part of an OPC model building and process/OPC qualification flow.
The setup of 1D measurements is straightforward, and simple 2D measurements can be made with traditional CD recipes. However, a great deal of time and effort must be devoted to both test pattern design and metrology setup in order to successfully measure complex 2D geometries. A method to extract the complete information content of a SEM contour on a 2D geometry of arbitrary shape is necessary to further reduce the time required for metrology setup and analysis of advanced patterning applications.
Large EPE variation not predicted by simulation can be important in detecting local fluctuations in patterning that could have a significant circuit influence. Topography or model inaccuracy can produce “pinching” or “bridging” events that may not be captured by simulation. A measurement system is required that can automatically measure EPE everywhere in the SEM image of a selected region for OPC evaluation, and then classify each EPE measurement result based on information from the design. In addition, accuracy of lithography simulations can be assessed by calculating the EPE between the measured SEM image and a simulation, instead of by using the design. In this case, the EPE results are an indication of model accuracy. Table 1 shows the OPC technology requirements for current as well as future nodes that will require contour-based calibration.
Layout verification and design flows are evolving toward the ability to simulate the focus exposure matrix (FEM) of the full chip to verify the printed shape as a process variability band . This capability has been enabled by full-chip simulation as well as the ability to perform design-rule and manufacturability checks on a simulated contour shape. The ability to capture and represent the true feature shape from a SEM image and convert it into the design environment (OASIS) for more checking is a key enabler in improving design. A fully automated EPE measurement function based on the design layout and the detected edges of the SEM image is a solution to these many issues.
Automated EPE measurement method
EPE measurement between design layout and the detected edges in the SEM image is effective in measuring the 2D features of the real pattern. However, several thousand EPE measurements are required to describe the complete information contained within a SEM image edge contour. It is impossible to manually place such a large number of EPE measurement boxes. To solve this issue, Hitachi High Technologies has developed a unique method to measure EPE of all edges in the SEM image automatically. The outline of the method is as follows (also shown in Fig. 1):
1) template matching between design layout and SEM image ;
2) EPE measurement boxes placed automatically along the detected edges in the SEM image;
3) correct edges detected from each EPE measurement box based on secondary electron (SE) intensity profile analysis;
4) EPE values are calculated from all EPE boxes; and
5) the EPE result reported as a SEM image overlaid with measured EPE and a text file including all EPE values from the image.
Figure 1. Automated edge-placement error (EPE) function comparing CD-SEM image and design intent.
Figure 2 indicates the experimental setup of this study. DesignGauge, which is a design-based metrology system developed by Hitachi High Technologies, is used to generate a recipe that performs SEM image acquisition and design template matching. A metrology request is generated with a site list of coordinates of critical areas for OPC model calibration and verification. After executing the recipe generated from this metrology request, SEM images with design template matching results are stored in DesignGauge.
Figure 2. Experimental setup of automated EPE measurement, using CD-SEM and design-template matching.
Automated EPE measurements are then performed post-processing using the stored SEM images. The automated EPE measurement function can generate a bitmap representation of the EPE results with the raw SEM image and a result file including all EPE values and the detected edge locations. The result file includes both the coordinate of the design edge and the feature edge as well as the EPE distance vector.
The EPE function allows for the automatic detection of all EPEs in an image. Each image can be analyzed independently or a set of images can be analyzed in batch mode. For this study, 164 SEM images were used to evaluate the effectiveness of both design pattern matching and EPE data content.
Currently, the EPE function is a post-measurement step. However, the function will be integrated into the next revision of DesignGauge. The EPE output result file is easily portable into many of the common OPC model building applications. The exact location of each specific EPE is determined by the layer and polygon number, and SEM-to-design pattern matching information. Each analyzed image typically contains 500-1500 EPE measurement values.
Due to the lithographic low-pass filter, corners have the largest EPE values. Corner rounding can be directly quantified, and the results indicate systematic variation along a long edge, so-called “ringing” from the proximity of the adjacent feature. In addition, line-edge roughness (LER) appears as a dominant source of variation in the results. Overall, the full image analysis using each individual EPE has provided a rich source of information that was not previously available.
Edge classification is critical for OPC and evaluation of OPC convergence. This is typically done by classifying the edges in the design in three ways: geometrically, by circuit function, and lithographically. For example, we can geometrically classify edges by the distance to a corner vertex and by edge length. Line ends can also be classified by observing the angle and length of the edges that abut the edge of interest; proximity to adjacent features is also a geometric classification.
As an example of circuit-function classification, the gate edges on a poly layer could be marked by doing a boolean with active areas or edges of poly that are critical to enclose a contact hole. Finally, the simulation of lithographic patterning can classify edges based on EPE, MEEF, or image properties such as maximum intensity. All these methods are typically used in an OPC script to prepare the target layer going into OPC and to evaluate the quality of the OPC produced; these are called ORC (optical rule checks).
This same classification methodology can help us interpret the EPE populations we can now obtain directly from silicon using the EPE estimation flow. A purely geometric classification of a poly layer, for which the distance to the corner vertex and the edge length were used to classify the design, can be used to analyze the EPE results obtained from a large set of images. These EPE results can be used to find sites that may not be patterning well or that are deviating from the target for specific classes of edges.
Table 2 indicates a summary of the EPE populations by class of edge. Of the roughly 160,000 measurements, most were long edges. These edges had a mean EPE value of -7.6nm, indicating the wafer was slightly over-exposed versus the target. Also, all of the short edges and corners have much higher variability in the EPE population. This is expected, but additional analysis is clearly needed to further classify the design edges and corresponding EPE populations.
Process variation quantification
Systematic and random process variability is the scourge of technology scaling. Systematic variability can prevent proper circuit functioning, significantly reduce yield, and easily go undetected without an awareness of what is killing the yield. Random variation can also reduce yield and transistor performance. With faster CPU speeds and scalable software for lithography simulation, it is now possible to simulate the FEM for a full chip and simulate much of the random and systematic sources of variability. This has enabled process-variability estimation and quantification via the process-variability band (PVband) . Figure 3 shows a simulated PVband with the target layer. The generation of this PVband is based on process models and the final mask design. It enables DRC-like checking of the process window and can also be used to find problematic layout events. The accuracy of the simulations used in generating these PVbands is often in question and relates directly to the validity of the conclusions reached by these “DFM” methods.
Figure 3. Simulated process-variability band (PVband) compared to the target, allows for checking of the process-window in a manner similar to traditional design-rule checks (DRC).
To address the accuracy concerns of dense contour simulations, a model calibration methodology by which the SEM image is contoured and converted into a polygon in the design space is proposed. Once the SEM contour is in the design space, several calibration methods are used to drive down the errors between measurement and simulation [4-6]. Also, the SEM contour can be studied directly, and a set of contours can be analyzed and converted into an empirical PVband. This process enables the same DRC checks that were developed for analysis of simulated PVbands to be used for those that are empirically generated.
For this example, 52 images of the same location were acquired and contoured using the EPE measurement flow outlined above. These SEM contours were then converted to an OASIS file. Figure 4 shows the raw contour of one image, the stacked set of contours for all 52 images, and a close-up image of the stacked SEM contours. A set of booleans were performed on these polygons to give the PVband, which can be overlayed with the target layer (Fig. 4d). Notice the larger variability at the line end and also the slightly irregular shape. The contours contain all LER information in addition to the contour information.
Figure 4. Empirical process variation estimation showing a) one empirical CD-SEM contour, b) 52 contours of the same location, c) close up of the 52 contours, and d) the final PVband overlaid with the original target.
If many images were taken at each process condition and the average contour was then plotted across the FEM space, the roughness component of the PVband could be eliminated. These shapes can now enter the normal error detection flow for PVbands using DRC.
Several caveats need to be considered when measuring SEM contours and placing this information into the design space. First, the quality of pattern matching directly influences the quality of the EPE measurements that result from this flow. While there is the option of manual over-ride of the automatic pattern matching, this is not very scalable as it requires direct human intervention. Random error sources in pattern matching or edge detection can be addressed with increased sampling to average out and obtain a more valid estimate of the contour; this is also done with 1D metrology by taking an average. Systematic error sources in pattern matching or SEM (magnification, scan linearity, scan rotation, matching offset) are more problematic ,as those errors will directly enter the measured EPE populations. This fact can make the EPE measurement methodology a good way of assessing SEM tool quality and test pattern design. Basically, the output EPE is only as good as the input image and pattern-matching result. The precision of the system needs additional study.
DesignGauge recipe automation enables the rapid acquisition of a large number of SEM images that are then aligned and directly associated with the design layout. The new image post-processing flow to produce EPE estimates based on exact CD-SEM edge-detection techniques enables a large amount of data to be extracted from each image. Raw SEM edge-location data can be directly input into the OPC model calibration flow. This method will be used to further advance mask generation and verification, and can analyze corner rounding, EPE population by class of edge, and empirical PVbands. Although many applications of this technique need to be explored, this study has demonstrated the power of design-based metrology by placing the SEM contour into the realm of the design. The data reduction of the large EPE population is a complex problem. However, more complete information from each SEM image can be used for OPC verification, design-rule analysis, and process evaluation/targeting. The ultimate benefit of design-based metrology can be realized.
The authors wish to acknowledge Hidetoshi Morokuma and Akiyuki Sugiyama of Hitachi High Technologies Corp. in Japan for their work on this paper. They would also like to acknowledge many useful discussions on the topic of metrology recipe generation at AMD and Hitachi. The authors would like to thank Yi Zou for aid with the PVband simulation and EPE-to-OASIS conversion portion of this paper, Takumichi Sutani and Brandon Ward for aid with image acquisition and running DesignGauge, and Takashi Iizumi, Brian Cunningham, and Chris Spence for their support of this development work.
1. C. Tabery, L. Page “Use of Design Pattern Layout for Automated Metrology Recipe Generation,” Proceedings of SPIE: Metrology, Inspection and Process Control for Microlithography XIX, Vol. 5752, pp. 1424-1434, 2005.
2. H. Morokuma, A. Sugiyama, Y. Toyoda, W. Nagatomo, T. Sutani, R. Matsuoka, “A New Matching Engine Between Design Layout and SEM Image of Semiconductor Device,” Proceedings of SPIE: Metrology, Inspection and Process Control for Microlithography XIX, Vol.5752, pp. 546-558, 2005.
3. J.A. Torres, C. N. Berglund, “Process Variations and Layout Design in IC Design,” Wireless Design and Development, http://www.wirelessdesignmag.com/, pp. 16, February 2006.
4. C. Haidinyak, C. Tabery, “Applications Using 2D Contact CDSEM Images,” 24th Annual BACUS Symposium, 2004.
5. Y. Granik, “Calibration of compact OPC models using SEM contours,” 25th Annual BACUS Symposium, 2005.
6. K.N. Taravade, E. Croffie, A. Jost, “Two Dimensional Image-based Model Calibration for OPC Applications,” LSI Logic web site, http://www.lsilogic.com/, pp. 1-6, 2003.
Cyrus Tabery is a member of technical staff in the RET/OPC development team at AMD. Advanced Micro Devices, One AMD Place, P.O. Box 3453, MS 78, Sunnyvale, CA, 94088-3453; ph 408-749-3599, e-mail firstname.lastname@example.org.
Lorena Page is metrology products department manager at Hitachi High Technologies America Inc., Pleasanton, CA; e-mail email@example.com.