The threshold voltages of CMOS transistors can vary significantly depending on their proximity to an implant well boundary. This well proximity effect (WPE) is caused by the well implant atoms that scatter laterally from the photoresist mask. From first principles of this scattering effect and detailed modeling, modifications to the mask were found that effectively suppress this induced variation in 90nm-node transistors. Consequently, circuit design can occur without having to create complex device models to account for WPE.
Igor Polishchuk, Nitish Mathur, Clifford Sandstrom, Pete Manos, Oliver Pohland, Cypress Semiconductor, San Jose, California
Managing process-design interactions becomes an ever-greater problem in the nanometer era of IC fabrication, resulting in design problems and yield losses. CMOS processing requires that the wells of two types (N and P) be created in specific areas of the wafer. It has been shown that during well formation, process implant atoms can scatter laterally from the edge of a photoresist mask and then land in the channel region of a nearby transistor . Such scattered atoms have an inadvertent effect on the Vt of that transistor .
To illustrate this problem, two otherwise identical transistors, formed in different relative locations to a well boundary (Fig. 1a), were examined. The bottom transistor is located far away from the well boundary and is unaffected by the lateral scattering of the well implant atoms, while the top transistor is surrounded closely by the well boundary and hence susceptible to the WPE.
Figure 1. a) Two otherwise identical transistors can have substantially different threshold voltages b) depending on their proximity to a well boundary.
Data show that only the edges of a transistor channel are inadvertently doped by the laterally scattered atoms, consequently only relatively narrow transistors are affected by WPE. In other words, wide transistors have substantially identical Vt (Fig. 1b), while the Vt of the narrow transistor varies significantly depending on the well boundary proximity. The fact that the Vt of a narrow transistor depends on the well boundary proximity is what distinguishes WPE from the traditional narrow-channel effect .
WPE becomes more severe with technology scaling as the space between transistors is reduced. At the 90nm node, WPE can contribute as much as 60mV to threshold voltage variation, making circuit design an extremely challenging task.
The only known solution has been the creation of sophisticated device models that predict MOSFET Vt based on specific design layout dependencies . Unfortunately, these models can be applied only after the layout of a circuit is complete. However, there is a critical need to perform circuit simulations early in the design process (prior to layout generation), based on schematics alone. Therefore, in addition to being quite cumbersome, attempting to add a Vt-shift device model to the design flow is also impractical. The only way to make the circuit design truly immune to this effect is through process solutions aimed at WPE elimination.
Simulating implant scattering
Figure 2a schematically depicts the WPE described above. The implant atoms (shown by arrows) on the left side of the structure penetrate deep into the silicon substrate forming a well. The implant atoms on the right side are stopped by the photoresist mask. The atoms that enter the photoresist layer near the mask edge (middle of the structure in Fig.2a) undergo random collisions and have a certain probability of escaping from the sidewall of the photoresist. These atoms then impinge on the wafer surface with a reduced energy and dope the channel region of a nearby transistor.
The corresponding WPE dopant profile obtained by Monte-Carlo simulation (TSUPREM4) is shown in Fig. 2b. The dopant concentration at the surface of the substrate is higher near the mask edge (darker shade in the figure) than farther away from the mask edge.
A more detailed study of the laterally scattered atoms was carried out by a TRIM simulator. This Monte-Carlo simulator enables the study of the atoms implanted into the target (mask) material. Specifically, it provides information such as position, velocity, direction, and energy of the backscattered atoms (atoms that are ejected from the photoresist layer). To find a process solution to WPE, we specifically focused on fundamental mechanisms behind this scattering.
Mask thickness effects. For the laterally scattered atoms to alter the Vt of a nearby transistor, they need to travel far enough from the mask edge, as shown in Fig. 2a. We first examine how the characteristic distance traveled by these atoms depends on the mask layer thickness. We define the scatter range as the region that contains 90% of the laterally scattered atoms, and if it is contained within the isolation region (shown in Fig. 2a) then the impact on the adjacent FET is minimal. The lateral scatter range increases from 0.1 to 0.45µm and is linearly proportional to the mask layer thickness over the range of 0.8-2.0µm.
Mask sidewall slope. We also examined the probability of lateral scattering depending on the slope of the photoresist mask. In the case of a vertical photoresist sidewall, a single collision is often sufficient to direct atoms out of the mask layer. However, since the direction of a scattered atom is barely changed in a single collision, multiple scattering events in the same direction are required in order to “eject” an implant atom out of the mask layer with a slight sidewall slope. Corresponding to this multiple-event process, the ejection probability decreases exponentially with the mask slope angle. Moving from a mask sidewall angle of 90° to ~80° effectively reduces the amount of lateral scattering by a full order of magnitude regardless of dopant species or implant energy, and an angle of ~70° results in another factor of ten reduction in scattering.
Figure 3. Simulation results show that atoms scattered far away from the mask hit the silicon surface a) with low energy, and b) at relatively large angles.
Energy and special distribution of scattered atoms. As illustrated in Fig. 2a, only those laterally scattered atoms that end up far from the mask edge affect the adjacent transistor (the rest of the laterally scattered atoms end up in the isolation region). Consequently, the atoms that alter the Vt of the adjacent transistor need to leave the photoresist at a considerable angle. In addition to this, as discussed above, these atoms have to undergo multiple scattering events, and as a result have their energy significantly reduced. The simulation results confirm that the well implant atoms that modulate the transistor’s Vt have a low residual energy and impinge on the surface at a relatively large angle (Fig. 3). This suggests that a relatively thin screening layer placed on the silicon surface can capture scattered atoms and effectively eliminate WPE.
Based on our understanding of the fundamental scattering mechanisms, several simple modifications to the process flow can effectively suppress WPE. First, the photoresist masking layer thickness should be reduced as much as possible. The minimum photoresist thickness will ultimately be limited by the requirement that the mask is capable of stopping the well implants. To circumvent this limitation, one can use a mask material with higher stopping power than that of photoresist. To optimize the process further, the mask thickness used for N and P wells can be tailored independently to the specific implant conditions.
Figure 4. Measured proximity dependant Vt variation is reduced from a) around 60mV in the original process to b) almost zero once a combination of WPE-suppressing solutions has been implemented.
Second, by finding an appropriate combination of photolithography process parameters, the slope of the resist profile can be reduced to 80°-85°, thus substantially reducing the amount of laterally scattered atoms.
Finally, a screen layer can be incorporated underneath the well mask to prevent the laterally scattered atoms from doping the substrate. There are several ways of introducing this screen layer into the process flow. It can be composed of a sacrificial material, which is removed, as is the mask itself, after well implantation. A good example is the bottom anti-reflecting coating (BARC) layer that is already often used as a part of the lithographic process. However, the screen layer can be a structural layer that is not removed, but instead used to build a transistor. For example, a polysilicon film can be first used as a screen layer, and later patterned to form the transistor gate.
While none of these approaches alone eliminates WPE entirely, a combination of them is effective in suppressing the well proximity effect. Figure 4 shows experimental results that indicate that transistor Vt distribution has become independent of the device proximity to the well boundary.
The detailed mechanism of WPE has been studied, and several practical methods of eliminating its effect have been demonstrated. The proposed solutions allow for further design rule shrinks and higher circuit density for future CMOS technology generations.
The authors would like to thank Dr. Rajat Rakkhit for his guidance as well as their colleagues in the R&D and Fab departments at Cypress Semiconductor.
- G. Hobler, S. Selberherr, “Monte Carlo Simulation of Ion Implantation into Two- and Three-dimensional Structures,” IEEE Trans. Computer-Aided Design, Vol. 8, May 1989, pp. 450-459.
- T.B. Hook, et. al, “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans. Electron Devices, Vol. 50, Sept. 2003, pp. 1946-1951.
- K.O. Jeppson, “Influence of the Channel Width on the Threshold Voltage Modulation in MOSFETS”, Electronic Letters, Vol. 11, July 1975, pp. 297-298.
- Presentations by TSMC and IBM at http://www.eigroup.org/cmc/minutes/.
Igor Polishchuk received his PhD and MS degrees in electrical engineering from the U. of California, Berkeley, and his BS degree from the California Institute of Technology. He is a senior staff engineer at Cypress Semiconductor, 198 Champion Court, San Jose, CA 95134; ph 408/545-7149, e-mail email@example.com.
Nitish Mathur received his bachelors in engineering from the Delhi College of Engineering, India, and his masters in science from the U. of Cincinnati. He is a staff technology development engineer at Cypress Semiconductor.
Clifford Sandstrom received his MS in chemical engineering from the U. of Minnesota and is a senior engineering manager at Cypress Semiconductor, Bloomington, MN.
Pete Manos received his BA in physics and his MEng degree in engineering physics from Cornell U. He is a member of technical staff at Cypress Semiconductor.
Oliver Pohland received his PhD in physics from the U. of Illinois and is a technology director at Cypress Semiconductor.