Exotic new nonvolatile memories look to challenge flash on cost
Some of those exotic new technologies being explored as alternatives to flash memory when conventional scaling hits a wall from 45nm now look like they may likely challenge traditional flash on cost before that, thanks to focus on new approaches that can be made with conventional CMOS processes. See below and p. 24 for three of these technologies.
Matrix extends 3D stacked memory for cheap 1Gbit memory die
Matrix Semiconductor reports that rethinking the architecture of its already unusual 3D layered memory array chip allows it to make a 1Gbit one-time programmable memory die using older-generation 0.15μm lithography. The die is only 31mm2, 3-4× smaller and accordingly cheaper than a flash chip made with the latest 90nm technology. This is double the density on the same size chip from Matrix last year.
“The net net is the scaling path for one-time programmable memory is actually very, very robust,” says Matrix COO Siva Sivaram. “Instead of doubling every 2-3 years as usual, we should be able to do a 20× shrink in five years.” That would bring prices down significantly, boosting the amount of memory one could buy for $4 over the next couple of years up to 1Gbit in 2007, from 256Mbit now. The company is initially targeting the market for portable digital content, and its memory chips are used in some of Sharp’s electronic dictionaries and in Mattel’s video players for kids. The 1Gbit chip it started sampling in May would extend video storage to ~2 hr.
Matrix saves silicon real estate by stacking polysilicon memory array layers on top of CMOS support circuits. The device is programmed by voltage that pops the antifuse on desired cells. It uses aggressive mask optimization to get very small pitch from the very simple masks for its crossbar array, which consist only of either straight lines in one direction or circles, pushing 0.18μm tools to make 0.13μm cells. The low-cost chips, made with plain old SiO2, W, and standard tools at TSMC, are shipping at the rate of more than 1 million units/month.
However, Matrix has realized that it doesn’t need to shrink the underlying transistors when it shrinks the array stack, so it can keep using older-generation technology for the supporting CMOS layers of the chip. For even its future 65nm memory array, it plans to use 110nm technology for the CMOS frontend. And now instead of the checkerboard array pattern with vias on each side of each square for its stacked memory cells, the company is moving to a segmented wordline architecture of long rectangles that can share vias at their ends, for a 23% improvement in density, gaining about a generation’s worth of shrink by the redesign. - P.D.
Elpida plans to use phase-change capacitors in DRAMs next year
Alternative technologies for memory that can also be erased and rewritten will take a little longer, but apparently not as long as once thought. While Intel and STMicroelectronics may be pursuing phase-change memory as a mainstream replacement technology for flash from the 32nm node when shrinks run out of steam, Elpida Memory says it plans to use phase-change chalcogenide film in some low-power DRAM capacitors starting as early as next year.
The company licensed Ovonyx’s GeSbTe thin-film technology earlier this year, already in use to record data on rewritable CDs and DVDs by changing the material between crystalline and amorphous states. Elpida’s Takao Adachi, CTO of the technology and development office, said the GST capacitors will cut DRAM power consumption by extending the time needed between refreshes down to once a month, for example, while also solving the reliability problems that typically occur with thinner capacitors. Adding the phase change layer only takes a couple of extra mask steps, and the company expects total production cost to actually be lower than conventional DRAMs, while speed remains about the same. Adachi noted they avoid the usual contamination problems by isolating the chamber used to make the GST film.
Samsung eases production of resistive memory with CMOS-compatible materials
Although Samsung seems to be working on almost all potential varieties of new memory, it’s talking with the most enthusiasm about its version of resistive memory. This discussion suggests Samsung’s OxRRAM process could be the candidate to replace flash when it reaches its scaling limit, possibly as soon as 2008. By using simple binary oxides, the process can deposit the film with current sputtering or CVD tools, though high operating current still remains a problem.
Instead of the perovskite materials like Ti and Zr usually used in resistive memory research, Samsung uses NiO, or other simple binary transition-metal oxides like TiO2, HfO2 or ZrO2, explained In-Gyu Baek, senior engineer on Samsung Electronics Co.’s process development team. Researchers have made an 0.18μm cell array with standard CMOS processes, where the cell is a sandwich of NiO between metal layers that stores data by changing its resistance. No special underlayers are needed. Applying a high-voltage pulse forms nanometer-scale circuits through the resistive metal oxide film, creating a material whose resistance then changes to a new level when current is applied, and stays there until reset by another pulse.
Even after 106 write cycles, Samsung’s NiO RRAM retains a 10-fold distinction in resistance between on- and off-states. The difference remains unchanged at >100× after 1012 read cycles. (Source: Samsung)
The 20nm NiO film requires forming voltage of <3V, and its resistance is set with 0.1 to 1mA in 10nsec, and reset with 2mA in 5μsec, at room temperature. Resistance in the two phases remains at least 1-2 orders-of-magnitude different through 1012 readings and 106 writings. Of most interest, resistance and reaction speed have almost no relation to cell size, suggesting the technology should be highly scalable, since even big variability in critical dimensions makes no difference in speed. The cells still consume too much power, so Samsung is investigating other oxide materials, and working on shrinking cell size from 4F2.
Also boosting enthusiasm for resistive memory is some recent progress in figuring out why it works. Researchers from Japan’s National Institute of Advanced Industrial Science and Technology (AIST) have been presenting results of a series of experiments that seem to confirm their model of the phenomenon. Akihito Sawa, of AIST’s Correlated Electron Research Center, said the strong interactions between electrons in these oxide films of peculiarly condensed matter mean that small changes in electrical field increase the Coulomb effects between atoms, which generates a huge response in resistance. Though some have explained this effect as a phase change from insulator to metal, researchers have shown that the effect is not actually in the insulator itself, but at the interface between the oxide and metal. AIST argues there may be a Schottky barrier at the metal-oxide interface, and the electrical pulse changes the height or width of the barrier to change the resistance.
Samsung suggests instead that electrons may flow or be blocked depending on the position of traps formed by bandgaps between the metal atoms and the crystal defects in the oxide. If traps are open, electrons collect and the cell resistance changes, switching from on to off. - Pennwell partner, Nikkei Microdevices