As transistors scale down in size, implant processes must accommodate requirements for lower energies and higher doses to improve advanced transistor performance. While scaling source/drain extension implants into the low-energy regime has attracted widespread attention, energy reduction of other implant applications is having a quiet yet significant impact. Two of these applications are now becoming critical - halo formation and gate-electrode doping - but because of specific issues associated with transistor scaling, the energy/dose combination for them is resulting in potential manufacturing bottlenecks that must be addressed.
Flexibility to perform implants over wide energy and dose ranges has always been important, but the need for it has increased significantly with time as energy ranges broadened, variable tilt capability became necessary, and an ever-increasing range of implant species was added. In the 1970s, implanters were classified according to the maximum ion-beam current, such that by the end of the decade, the medium-current (MC) and high-current (HC) segments were well established [1, 2]. By the mid-1980s, a third type, high energy (HE), was differentiated by the maximum achievable ion energy [2, 3].
Figure 1 shows a clear migration to lower energy beginning in the late 1980s. The change in total energy range went from just over one order-of-magnitude in 1976 to more than four orders-of-magnitude 30 years later. Besides the increase from one to three implant system types, there have also been significant energy range increases within each type, particularly for HC and MC.
Tools in the HC segment dropped into the low-energy regime in 1995 and quickly went further into the sub-keV range (at the expense of capability above 80keV). MC systems migrated to low energy (at 3keV) a couple of years before HC and have continued on a path to lower energies at a slower rate. The latest systems operate down to 1keV and effectively lower by using molecular species .
Lower energy, quite simply, is the most fundamental trend in ion implantation. As transistor gate length decreases, all other transistor dimensions (from extension junction depth to gate thickness) also decrease. Implanting ions at low energy to achieve shallower junctions and more abrupt profiles has been a key factor in enabling continued technology-node scaling.
Figure 2. Schematic cross-section of the super-halo structure, applied to a partially depleted SOI transistor .
Halo design is a critical element in advanced transistor scaling, with profound implications for ion implanter development. The so-called super-halo (Fig. 2), in which a highly nonuniform dopant profile is self-aligned to the gate in both lateral and vertical dimensions, has been widely adopted since it was proposed for sub-50nm devices . It offers superior short-channel effects (SCE) down to 25nm gate length, helps compensate for the slowing of gate-dielectric thickness scaling, and reduces device sensitivity to junction depth variations .
Transistor designers also have used super-halos effectively in partially depleted silicon-on-insulator (SOI) , where higher doses improve SCE without increasing junction capacitance to unacceptable levels. Because super-halos require steep dopant profiles in 25-50nm gate-length transistors, halo implant energies are decreasing while doses are increasing. Feudel et al.  have described the importance of “heavily doped low-energy halos” along with low-diffusion activation to obtain high performance in 35nm gate-length transistors, for example.
High-tilt halo implants, typically in the low-to-mid 1013/cm2 dose range, have traditionally been run on MC implanters. The use of the more shallow, more abrupt super-halo implants affords an opportunity to re-evaluate technology options. One obvious solution, using heavier mass species such as indium and antimony, has been widely investigated and would seem to make good sense given that the higher mass species enable shallower, more abrupt profiles without pushing implanters into the low-energy regime. Limited activation due to solid solubility  for these species has prevented their widespread use, however, especially because higher doses are required. Instead, chipmakers have focused on traditional species, including boron super-halos for nMOS devices.
The use of boron, however, pushes the super-halo application into the low-energy (<5keV) regime. Lower energy, plus dose increases to high 1013/cm2 or even low 1014/cm2, creates a productivity problem on conventional MC implanters. One solution is to move the application from a conventional MC machine to a single-wafer, high-tilt HC platform. In general, process control is sacrificed as a tradeoff for higher beam current.
An alternative approach is to extend the MC technology that has historically been effective for halo implants into the super-halo (i.e., low-energy mid-dose) regime. This solution offers energy purity for abrupt channel profiles, angle control well below 0.5° for accurate dopant placement, and dosimetry to maintain threshold voltage control. This approach provides super-halo process control at a reasonable throughput for production fabs, without sacrificing the broad energy range that enables a wide variety of channel and well implants.
Extracting and transporting ions at a relatively high energy followed by deceleration to the final energy is useful as long as high-energy neutral species are removed from the beam. With filtered deceleration, a low-energy mid-dose system can extract ions at 20keV or more to increase low-energy beam current while producing clean low-energy dopant profiles. In Fig. 3, a 1.0keV boron profile into preamorphized Si is indistinguishable from a drift (nondecelerated) profile generated using an HC machine. Note the lack of detectable energy contamination in the filtered mid-dose profile compared to that of an HC system using in-line deceleration - even when energy contamination is <1%. Energy contamination such as this cannot necessarily be tolerated in a super-halo structure requiring sharp dopant profiles.
Continued gate-electrode thickness scaling also has important consequences for ion implantation in the high-dose regime. Assuming a gate thickness between one and two times the gate length, the International Technology Roadmap for Semiconductors (ITRS)  calls for a gate thickness of 32-64nm in 2005, decreasing to 25-50nm by 2007. Thinner polysilicon gate electrodes translate directly to lower-energy implant, with pMOS transistors being more critical because the dopant species are lighter. To avoid unwanted effects due to fluorine, elemental boron is still the dopant of choice for pMOS poly gates, and the use of thinner polysilicon films combined with the higher doses necessary to reduce polysilicon depletion has pushed the doping processes into a critical regime .
Because the transistor channel is immediately below the gate, poly gate doping processes are very sensitive to energy contamination compared to extension implants. Energy contamination <1%, commonly accepted for extensions, is far too large for gate doping. At a dose of 4×1015/cm2, for example, 0.5% energy contamination can place a dose of up to 2×1013/cm2 directly into the channel - a significantly higher dose than most threshold-voltage adjustment implants. Consequently, chipmakers want energy contamination to be essentially undetectable for their advanced low-energy poly-gate doping processes.
The low-energy requirements are illustrated in Fig. 4, which shows the ITRS gate-electrode thickness values and relevant boron implant depths by year. The boron implant energy must be selected so that the profile tail does not extend into the transistor channel. Keeping the implant projected range (Rp, the depth at which the peak of the profile occurs) plus 4×-5× the longitudinal straggle (σ) within the polysilicon film ensures that the channel will remain unperturbed. (Of course, diffusion during the dopant activation anneal is another process that must be properly engineered and controlled.) In Fig. 4, the shaded bands represent Rp + 4 - 5σ for boron implant energies of 1-4keV.
Assuming gate electrodes of the maximum thickness, 4keV B+ is acceptable in 2005 (for 65nm technology), but energy will decrease to 3keV in 2007 (45nm) and 2keV in 2009 (32nm). Energy could be even lower, 1keV in 2009, for a process with a minimum ITRS polysilicon gate-electrode thickness. The combination of low energy, high doses in the mid-1015/cm2 range, and zero tolerance for energy contamination places new demands on implanters for gate-electrode doping.
The transition to metal gates, projected for 45nm or 32nm technology, does not necessarily eliminate the problem. One of the leading metal-gate candidates, fully silicided material, utilizes implantation of thin polysilicon with conventional species (B, P, or As) prior to metal deposition and conversion to silicide . The high-concentration dopant migrates to the gate/gate-dielectric interface during the silicidation process, altering the work function of the material at the interface. In this way, a single metal such as NiSi may be used for both nMOS and pMOS transistors. Because the process includes an ion implant into the polysilicon film, the issues regarding low-energy, high-dose throughput and energy contamination sensitivity are the same as for poly-gate electrodes.
Fortunately, several iterations of multiwafer HC beamline development have resulted in machines that produce 7mA of drift B+ beam current at 2keV - enough to implant 50×300mm wafers/hr with a dose of 2×1015/cm2. With short beamlines and high beam utilization, multiwafer systems have a significant advantage for low-energy, high-dose processes. In the long term, single-wafer, high-dose implant technology will have to mature to match multiwafer productivity without energy contamination.
Using molecular species such as decaborane (B10H14)  or octodecaborane (B18H22) that allow implanters to run at ~11-20× higher energy with only ~5-10% of the beam current is another potential option. Additionally, further development in gate-electrode dopant activation - for example, by using laser annealing to increase active dopant concentration at the gate-dielectric interface  - may influence implant processes for this application in the future.
For more than 15 years, new technology has enabled ion implanters to operate at ever-lower energy levels in order to continue transistor scaling. While the original driver for low-energy implant, the ultrashallow source/drain extension, is well known, continued scaling issues such as short-channel and poly-gate depletion effects have now forced implants such as halo formation and gate-electrode doping into a low-energy regime, where traditional implanters struggle to keep up with high-volume production. To address these applications, low-energy implanters must operate more effectively at either mid- or high doses. Ion implantation, valued especially for its flexibility and ease of process integration, will no doubt remain a critical component in advanced transistor fabrication for nodes to come.
The authors gratefully acknowledge many stimulating discussions with Aditya Agarwal, Mike Ameen, Hans Gossmann, Mark Harris, Ken King, John Morgan, Robert Rathmell, and Bo Vanderberg of Axcelis Technologies. This article would not have been possible without their help and guidance.
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T.M. Parrill received his BS in metallurgical engineering and materials science from the U. of Notre Dame and his PhD in materials science and engineering from Northwestern U. He is an advanced technology manager at Axcelis Technologies, 108 Cherry Hill Dr., Beverly, MA, 01915; ph 978/787-4000, fax 978/787-4200.
L.M. Rubin received his BS in materials science and engineering and his MS and PhD in electronic materials from the Massachusetts Institute of Technology. He is currently a senior scientist at Axcelis Technologies.