Increasing speed and functionality in ICs place severe demands on current interconnects in terms of speed (bandwidth), power, and density. Innovations in conventional conductors and insulators, along with traditional device scaling, will soon fail to satisfy performance requirements. New solutions - three-dimensional device architectures, coplanar waveguides, radio-frequency, and optical interconnects (OI) - are needed.
OIs could be beneficial in short-scale IC applications, due to wide bandwidth, reduced loss, and low crosstalk. In particular, the optical telecom single-channel bandwidth is 40Gbit/sec, far above that in electrical wires. In recent years, OIs have witnessed a desirable length reduction from intercontinental telecommunications to local area networks and individual computer systems. Further miniaturization could lead to OI incorporation into Si ICs.
Figure 1. 3D optical interconnect schemes.
This article reviews OI research opportunities and applications at the College of Nanoscale Science and Engineering of the U. at Albany using the 3D free-space OI platform shown in Fig. 1. This platform allows a new IC architecture that takes full advantage of massively parallel architectures. The 3D architecture consists of arrays of vertical-cavity surface-emitting lasers (VCSEL) and detectors connected through a reconfigurable optical medium. It provides the highest interconnect density because photons virtually do not interact with each other and can occupy the same point in space .
Integrating optical transmitters
Optical transmitters present the greatest challenge to integration into Si electronics.
Growth of compound semiconductor optical transmitters directly on Si has failed due to material and process incompatibilities. Success could be achieved through “indirect” integration in which optical emitter arrays are interfaced to Si electronics after fabrication on appropriate substrates. One promising technology for VCSEL integration with Si is “oxidation lift-off,” as recently developed and demonstrated by the Albany team.
When comparing state-of-the-art VCSEL operating parameters with off-chip I/Os target specifications from the International Technology Roadmap for Semiconductors, one issue is that optoelectronic components operate at lower temperatures than Si ICs. Although schemes involving heatsinks or coolers could address thermal incompatibilities, resulting complexities might preclude chip-level OIs. The ideal solution requires VCSELs that function reliably at the operating temperature of Si ICs (~100°C). The direct modulation frequency of present VCSELs poses another challenge because it satisfies current Si IC needs, but is not scalable to future generations of Si chips.
Current VCSEL operating characteristics are bound primarily by the use of quantum well (QW) active media, whose performance is approaching theoretical limits. The simple, inexpensive, and effective integration of optical emitters with Si electronics requires novel active media that overcome fundamental limitations of QWs.
Quantum dots (QD) are one such novel alternative. QDs are ensembles of nanoscale 3D particles of narrow-bandgap material embedded within a wide-bandgap semiconductor, and can produce a discrete atomic-like electronic spectrum. In 1982, Arakawa and Sakaki predicted that a dimensionality reduction from QWs to QDs could produce a significant increase in thermal stability, and that it could yield a maximum differential gain increase of three orders-of-magnitude; this gain directly determines modulation bandwidth.
Fabricating quantum dots
The predictions noted previously were experimentally demonstrated at low temperature (<100K), where carriers are strongly localized in the QDs and discrete energy levels prevent thermal spreading. At Si IC operating temperatures, localization is inhibited due to carrier excitation to higher excited levels and barrier, and associated benefits disappear. To maintain localization at higher temperatures, the separation between ground and excited levels, as determined by barrier height (size) and shape of the QD, must be increased above thermal energy.
QD height and shape are controlled primarily by fabrication methodology. QDs are formed by self-assembly in epitaxial heterostructures with high lattice mismatch, grown usually by molecular beam epitaxy (MBE). Most explored are InAs/GaAs heterosystems with 7% lattice mismatch. A single QD energy level is extremely narrow (~10µeV). Self-assembly yields varying QD sizes, however, leading to relatively wide, inhomogeneously broadened emission and gain spectra.
Also, all-epitaxial InAs QDs on GaAs or AlAs exhibit pyramidal or near-pyramidal shapes, caused by the surface energy of the growing InAs, resulting in poor electron-hole interactions and marginal optical gains. QDs with more symmetric shapes (e.g., spheres) increase electron-hole interactions and enhance maximum gains.
Nanoscale shape engineering can form QDs with symmetric shape and uniform size (volume) distribution and, therefore, higher saturated gain and differential gain. Further enhancements are achieved by increasing the total number of QDs by adding more layers in the heterostructure, and fabricating resonant-tunneling QW-QD structures by placing QDs close to a carrier-collecting QW layer.
The application of lithographic patterning to control QD synthesis has been shown to reduce inhomogeneous broadening of QDs but it leads to high defect density and poor quality. Instead, the Albany team has developed simple MBE nanoengineering approaches for thermodynamics-driven QD self-assembly. These approaches allow management of size, density, and shape, and control of both homogeneous and inhomogeneous electronic spectra and transient phenomena in InAs QDs.
Figure 2 illustrates the basic elements of the nanoengineering concept. QDs are embedded in short-period superlattices (SPSL) with (AlAs)2ML/(GaAs)8ML periodicity (ML = monolayer). The SPSL mimics the properties of AlGaAs, enhances material quality, and allows reliable control of In adatoms’ surface kinetics on atomically sharp GaAs or AlAs.
Self-assembly of QDs occurs through a 2D to 3D phase transformation almost instantaneously after deposition of a ~1.5 ML InAs “wetting” layer. Thermodynamically driven coarsening of the 3D islands and In segregation on their surface are prevented by QD capping with 2 ML-thick AlAs layers. The low surface mobility and segregation coefficient of Al effectively “freezes” the QD-containing growing surface.
Shape engineering is achieved by “overgrowing” QDs covered with 2 ML AlAs with a GaAs layer at a thickness corresponding to the QD height (~6nm). Due to high mobility of Ga adatoms, GaAs will mainly cover the low-stress area between QDs. The sample is then rapidly heated by 100°C, resulting in In redistribution mainly from the QD tops, thus controllably modulating shape and volume. Finally, a thin layer of GaAs is grown to complete the SPSL .
The outcome is symmetrically shaped, AlAs-covered QDs consisting of truncated pyramids with flat tops. Such truncated ensembles exhibit improved volume uniformity because larger QDs lose more In, leading to inhomogeneous broadening of the emission spectrum down to 29meV. The symmetrical shape also increases electron-hole coupling, causing higher emission efficiency and saturated ground-state gain. AlAs capping yields a ground to first excited-state energy separation of ~90-100meV, considerably higher than the thermal energy.
Truncation reduces structural roughness and provides noticeable advantages in multilayer QDs, resulting in smooth-top SPSL interfaces (Figs. 2b, 2c) - as opposed to wave-shaped SPSL for nontruncated QDs - higher optical performance, and, most important, enhanced thermal stability.
QD characteristics and performance
Figure 3a plots threshold current density vs. temperature for laser diodes made with QWs and nontruncated and truncated QDs. The latter demonstrates unsurpassed thermal stability with 219°C maximum lasing temperature and extremely high characteristic temperature To = 380K up to 60°C . Lasing characteristics at 1.22µm were extremely high, including a medium room-temperature threshold current density of 56A/cm2, and saturated modal gain as high as 16cm-1. A novel tunneling, triple-layer, truncated QD structure produced modal gain of >50cm-1, sufficient for implementation in all-epitaxial VCSELs.
Strong localization at high temperatures in nanoengineered QDs yielded more than two orders-of-magnitude higher defect tolerance than QWs at room temperature (Fig. 3b). Luminescence thermal-quenching analysis yielded a very high activation energy of 450meV, corresponding to electron escape from QDs to SPSL barriers. Improved QD defect tolerance should provide longer device lifetime and better reliability in QD lasers.
Nanoscale engineering by the Albany team has successfully produced a QD medium with the characteristics required for successful integration of QD optical transmitters with Si electronics at the operating temperature of Si ICs. Concurrently, Bhattacharya et al. have shown that QDs are capable of achieving a bandwidth as high as 43GHz, a value unreachable by QWs.
It is therefore projected that the demonstration of miniature QD VCSELs with the target modulation, thermal properties, and reliability will occur in the next few years.
Due to cost, the most probable application for “OI-on-Si” will be a communication chip combining logic with active optical components for fiber-based LANs. This application is less demanding than interchip links and might represent an economically viable insertion point for optics into Si ICs.
This work is supported by MARCO and DARPA through the Interconnect Focus Center Program and the National Science Foundation under grant number ECS-0334994.
- S. Oktyabrsky, J. Castracane, A. Kaloyeros, Proc. SPIE, Vol. 4652, p. 213, 2002.
- V. Tokranov, M. Yakimov, A. Katsnelson, M. Lamberti, S. Oktyabrsky, Appl. Phys. Lett. 83, p. 833, 2003.
Alain E. Kaloyeros received his PhD from the U. of Illinois, Urbana-Champaign, and is VP, chief administrative officer, and professor at the College of Nanoscale Science and Engineering, U. at Albany-SUNY, Albany, NY 12203; e-mail email@example.com.
Serge Oktyabrsky received his PhD from Lebedev Physics Institute, Moscow, Russia, and is associate professor at the College of Nanoscale Science and Engineering.