To overcome design limitations identified with conventional bulk micromachining and material limitations identified with the standard surface-micromachining process, the MOEMS Manufacturing Consortium, formed within the National Institute of Standards and Technology's (NIST) Advanced Technology Program (ATP), developed a hybrid process based on micromachining a silicon-on-insulator (SOI) wafer, which is used in an add-on polysilicon surface-micromachining process after planarization.
In contrast to the standard metal-oxide-semiconductor and bipolar processes that are used in IC manufacturing, developers of microelectromechanical systems (MEMS) typically use application-specific processes that are developed for each device configuration. The closest approximations to standard processes in this field include bulk micromachining, in which material is selectively removed from the bulk of a silicon wafer using various wet and dry etching techniques; and surface micromachining, in which thin-film layers are repetitively deposited and patterned, similar to thin-film processes in IC manufacturing. While the properties of bulk-micromachined devices composed of single-crystal silicon (SCS) have excellent and reproducible materials properties (Young's modulus, Poisson's ratio, lack of residual stress and stress gradients) and electrical properties (ability to control conductivity over five orders-of-magnitude), this process has limitations in the geometrical shapes that can be formed.
Comparing bulk micromachining processes
Typical bulk micromachining processes involve anisotropic wet-chemical etching, where the geometries of the components are bound by the slowest etching crystallographic planes. This limits the obtainable geometries to v-groove trenches and inverted pyramidal structures on the (100) crystallographic face of common silicon wafers. While anisotropic deep reactive-ion etching based on the Bosch process has relaxed this constraint to some degree, it is only applicable to structures defined in the plane of the wafer.
Figure 1. Stress-induced curvature of a released polysilicon Fresnel lens lifts it out of the plane of the wafer. (Sources: M. Rosa, D. Sun, Xerox)
In contrast, surface micromachining has the capability to fabricate arbitrary geometries in the plane of the wafer, including the ability to release structures and rotate them out of the plane of the wafer. This versatility has enabled the production of many different optical MEMS structures . Nonetheless, this process has not been optimized for optical applications, and optical components fabricated using this process often exhibit both static curvature induced by residual stress and stress gradients in the deposited films as shown in Fig. 1, and dynamic curvature, associated with bending of thin elements subjected to high accelerations.
Bulk micromachined optical components, however, have no residual stress or stress gradients in the absence of high doping levels and deposited thin films, and the thickness of the components is limited only by the thickness of the wafers from which they are fabricated. To overcome design limitations identified with conventional bulk micromachining and material limitations identified with the standard surface-micromachining process, the MOEMS Manufacturing Consortium (Corning IntelliSense, Coventor, Maxim Integrated Products, Microscan Systems, Optical Micro-Machines, Standard MEMS, and Xerox) was formed within the National Institute of Standards and Technology's (NIST) Advanced Technology Program (ATP) in 1999–2003 to develop a robust manufacturing process that combines the strengths of these two fabrication processes and avoids their limitations . This hybrid process is based on micromachining an SOI wafer, which is then used in an add-on polysilicon surface-micromachining process after planarization (Fig. 2).
The SCS device layer is used for critical optical and electrical components. The benefits of SCS layers for optical applications have been confirmed by a number of research groups that have used wafer-bonding techniques to incorporate an SCS mechanical layer [3, 4]. By starting with an SOI wafer, this additional wafer-bonding step can be avoided. The SOI device layer has a user-specified thickness that can be selected for a given application, and has excellent, reproducible electrical and mechanical thin-film properties. By combining a bulk-micromachining SOI process module with a polysilicon surface-micromachining module, the design freedom (hinges for out-of-plane components, electrodes) and enhanced manufacturability (anchors to eliminate timed etch and dimples to avoid stiction) enabled by surface micromachining of polysilicon can be coupled with the excellent electrical and mechanical properties of bulk micromachined SCS to obtain the benefits, yet avoid the weaknesses, of these two different processes. In addition to optical applications, SOI also benefits micro-robots , RF resonators , resonant strain gauges , inertial sensors , and real-time thermal scene simulators .
To ensure that the process sequence is flexible and broadly enabling, a group of diverse end users with applications in optical switching for telecommunications (Optical Micro-Machines), machine vision for clinical analysis (Microscan Systems), and printing (Xerox) partnered with infrastructure suppliers in foundry services (Standard MEMS and Corning IntelliSense) and modeling and simulation (Coventor), to develop a common process and design environment for device manufacturing based on the semiconductor foundry model. All of the end user applications were fabricated on the same wafer using the same process sequence.
Hybrid SOI-MEMS micromachining process
The hybrid SOI-MEMS micromachining process sequence combines bulk and surface-micromachining process modules, benefiting from their strengths and avoiding many of their weaknesses . A tetraethyl orthosilicate (TEOS) trench fill and chemical mechanical polishing (CMP) step forms the interface between these two process modules. An overview of the intermediate hybrid process sequence is shown in Fig. 3. The starting SOI wafer is shown in Fig. 3-1. An SOI wafer is used to yield reproducible material properties (Young's modulus, Poisson's ratio), optically flat surfaces, high-Q components, and potentially thick layers that are rigid enough to withstand stresses created by deposited layers.
Figure 3. The hybrid SOI micromachining process: 1) SOI wafer; 2) DRIE etches through the SCS layer for anchors and dimples; 3) timed etch of buried oxide layer for the formation of dimples; 4) polysilicon deposition and blanket etch back to anchor released SCS components to the handle wafer, and to form polysilicon dimples; 5) DRIE through the SCS layer to form released SCS components; 6) TEOS fill and CMP; 7) anchors to the SCS layer; 8) dielectric isolation; 9) polysilicon structures; 10) windows down to the SCS layer for mirrors that are to be metallized; 11) metallization; and 12) sacrificial release (wet or dry). (Source: P. Gulvin, Xerox)
Holes are etched into the active silicon (Fig. 3-2) and into or through the buried oxide below (Fig. 3-3), and then are refilled with polysilicon (Fig. 3-4). If the buried oxide is completely removed, then the polysilicon acts as an anchor to the substrate. If the buried oxide is only partially removed, then the polysilicon forms a protrusion from the bottom of the active silicon that acts as a dimple for preventing stiction, as is seen in standard surface-micromachining processes.
Holes are etched into the silicon to form the desired silicon structures (Fig. 3-5). The wafer is then planarized with a TEOS deposition and CMP to eliminate large topography that would make further lithography difficult (Fig. 3-6).
The process sequence then switches to a purely surface-micromachining process module. Vias to the silicon layer are etched to allow subsequent layers to anchor (Fig. 3-7). Silicon nitride is deposited to allow electrical isolation (Fig. 3-8). Polysilicon is deposited to form tops of hinges, electrode plates, caps for tops of sliders, and bridges for traces (Fig. 3-9).
Additional holes to the silicon are created (Fig. 3-10), and metal is deposited to form the traces and bond pads, and to act as the reflective surface on mirrors (Fig. 3-11). Optionally, two different metal thicknesses can be used: a thick metal optimized for electrical conductors, and a thin metal for mirror surfaces.
The wafers are then diced, sorted, and shipped to the user for release (Fig. 3-12).
By using this hybrid combination of bulk and surface-micromachining modules, all of the strengths listed previously are combined, and most of the weaknesses are mitigated. The hybrid SOI-MEMS micromachining process is based on the use of process modules as building blocks for process sequences. The basic building blocks are shown in the table.
Rapid prototyping process sequence
The rapid prototyping process sequence, using only two mask layers (SCS and thick metal), allows designs to be quickly created and fabricated in order to rapidly test ideas such as new actuator designs. Features are defined in the SCS device layer, and will be released in a timed etch of the buried oxide layer that is exposed by the SCS etch. The buried oxide etches at ~1µm/min, so that features W µm wide can be released in a sacrificial wet HF etch that is slightly over W/2 min. Features such as wires and bond pads that are defined in the device layer will remain anchored to the substrate through the buried oxide layer so long as their dimensions are significantly >W/2µm.
SOI micromachining process sequence
The SOI micromachining process sequence makes use of the entire SOI bulk-micromachining process module. This process sequence can be used for designs that do not require released polysilicon. Since the polysilicon that is used for dimples and anchors is not released, it does not require a high-temperature thermal budget for stress relief, enabling monolithic integration of microelectronics in a microelectronics-first approach to MEMS integration.
Intermediate hybrid process sequence
The intermediate hybrid process sequence adds on a polysilicon surface-micromachining process module after the topography created in the SOI bulk-micromachining process module has been planarized by a TEOS trench-fill, followed by CMP. The TEOS is a sacrificial oxide layer removed during the final release etch. This module adds on many of the capabilities of a multilayer polysilicon surface-micromachining process, such as out-of-plane motion using hinges or bearing pins. Through combination with the SOI bulk-micromachining process module, single-crystal elements such as mirrors, diffraction gratings, and Fresnel lenses can be released.
Compared to the standard UC Berkeley/MCNC-MUMPs three-layer polysilicon process, in which released parts are defined in poly 1 and rotated out-of-plane on hinges defined in poly 2, here the SCS device layer of the SOI wafer is used to make the critical released parts instead of poly 1. In this way, the released parts have superior SCS materials properties.
Advanced optical process sequence
The advanced optical process sequence adds on the advanced optical module that includes etches optimized for optical applications, as well as patterned doping and thin metallization for optical structures. The timed etches of the SOI device layer allow fabrication of free-space grating structures and ridge waveguide structures. Patterned doping allows the SCS to be used as an electrical conductor (wires, thermal actuators), where doping is required to minimize electrical losses and drive voltages, and as an optical conductor (waveguides), where doping is to be avoided to minimize optical losses .
Finally, the advanced optical module includes a thin metallization layer optimized to increase the optical reflectivity of mirrors, while minimizing mirror distortions caused by the thicker metal layer optimized for electrical conductors and bond pads. Some examples of structures that have been fabricated previously in the hybrid SOI micromachining process and advanced optical process are shown in Fig. 4.
Figure 4. Examples of MOEMS devices that have been previously fabricated in the hybrid SOI-MEMS micromachining process sequences: a) flip-chip bonding of a III-V laser diode (Source: M. Rosa, D. Sun, Xerox); b) advanced optical process with released waveguides and thermal actuators (Source: Larry Herko, Xerox); c) released SCS mirror (Source: S. Bakshi, E. Carlen, K.-H. Heng, Corning IntelliSense); and d) thick SCS mirror, thin polysilicon lock, and dimples.
The MOEMS Manufacturing Consortium has developed a new fabrication process using SOI wafers as the starting substrate in a surface-micromachining process. This process enables the fabrication of critical optical, electrical, and mechanical components in the SCS device layer. The process includes the capability for hybrid integration of optoelectronic elements, such as laser diodes and photodetectors, using flip-chip bonding and the capability for monolithic integration of microelectronic elements, such as drive transistors, using a CMOS/DMOS process that is compatible with the MEMS elements. The process is now generally available at the Infotonics Technology Center (www.infotonics.org), a not-for-profit organization located in Canandaigua, NY.
Work was performed under the Cooperative Agreement #70NANB8H4014, NIST ATP and was performed in part at the Cornell Nano-Scale Science & Technology Facility, which is supported by the National Science Foundation under Grant ECS-9731293, its users, Cornell U., and Industrial Affiliates. The author would like to thank contributors from Clarkson U. (S.V. Babu, Sharath Hedge), Corning IntelliSense (Shivalik Bakshi, Jonathan Bernstein, Edwin Carlen, Clifford Fung, Khee-Hang Heng, Christos Monovoukas, Michael Teague), Coventor (Stephen Bart, John Gilbert, Charles Hsu, Mike Jamiolkowski, Tom Korsmeyer, Art Morris, Ted Plowman, Vladimir Rabinovich), Maxim Integrated Products (Janusz Bryzek, David Burns, Steven Nasiri), Microscan Systems (Troy Daiber, Malinda Elien, Bruce Sharf, Andrew Zosel), Optical Micro-Machines (Li Fan, Ken Gabriel, Jim Hartman, Anis Husain, Ming Wu), Rochester Institute of Technology (Alan Raisanen), Standard MEMS (Flora Briganti, Gene Burke, Ken Chin, Steve Delvecchio, John Fijol, Glenn Fricano, Nena Golubovic, Dave Kharas, Raji Mali, Mike McEntee, Chris Nichols, Tom Pumo, Abdoul Seck, Veera Veeraraghavan, Shifang Zhou), and Xerox (Jennifer Benson, Cathie Burke, Jim Calamita, Jets Chang, Jingkuang Chen, Chris Chua, James Diehl, Dirk DeBruyker, Elliott Eklund, Kathleen Feinberg, Kristine German, Peter Gulvin, Larry Herko, Nancy Jia, Chuang-Chi Lin, Pinyen Lin, Xueyuan Liu, Robert Lofthus, Jun Ma, John Meyers, Bill Nowak, Peter Nystrom, Feixia Pan, Eric Peeters, Michel Rosa, Yi Su, Decai Sun, Alex Tran, Yao Rong Wang) who have helped develop the process and devices in this article.
- M.C. Wu, "Micromachining for Optical and Optoelectronic Systems," Proc. IEEE, Vol. 85, pp. 1833–1856, 1997, and references therein.
- J.A. Kubby on behalf of the MOEMS Manufacturing Consortium, "Combining Light with Motion: Hybrid Integration of Light Emitters and Detectors with SOI-based Micro-opto-electro-mechanical (MOEMS) Systems," Proc. SPIE, Vol. 4293, p. 32, 2001.
- G.-D. J. Su, H. Nguyen, P. Paterson, H. Toshiyoshi, M.C. Wu, "Surface-micromachined 2D Optical Scanners with High-performance Single-crystalline Silicon Micromirrors," Proc. CLEO, post-deadline paper CPD-21, May 2000.
- R.A. Conant, J.T. Nee, K.Y. Lau, R.S. Muller, "A Flat High-frequency Scanning Mirror," Proc. Solid-State Sensors and Actuators Workshop, pp. 6–9, June 2000.
- S. Hollar, A. Flynn, C. Bellew, K.S.J. Pister, "Solar Powered 10mg Silicon Robot," MEMS 2003.
- T. Lamminmaki, K. Ruokonen, I. Tittonen, T. Mattila, O. Jaakkola, et al., "Electromechanical Analysis of Micromechanical SOI-fabricated RF Resonators," Proc. Modeling and Simulation of Microsystems Conf., p. 166, p. 217, 2000.
- S.P. Beeby, G. Ensell, B. Baker, M.J. Tudor, N.M. White, "Micromachined Silicon Resonant Strain Gauges Fabricated Using SOI Wafer Technology," IEEE J. Microelectromechanical Systems, Vol. 9, No. 1, pp. 104–111, March 2000.
- http://www.analog.com/UploadedFiles/Product_Briefs/277445242MEMS product_highlights.pdf.
- J.D. Popp, B. Offord, R. Bates, H.R. Marlin, C. Hutchens, et al., "A Real-Time Infrared Scene Simulator in CMOS/SOI MEMS," http://www.spawar.navy.mil/sti/publications/pubs/td/3117/129.pdf.
- P. Gulvin, Hybrid Silicon-On-Insulator Micromachining Process, Design Guide, 8-Mask Version, 2004.
- K. German, J. Kubby, J. Chen, J. Diehl, K. Feinberg, et al., "Optical MEMS Platform for Low Cost On-chip Integration of Planar Light Circuits and Optical Switching," Proc. SPIE, Vol. 5357, submitted for publication.
Contact Joel Kubby at the Xerox Wilson Center for Research & Technology, ph 585/422-9609, e-mail jkubby@.crt.xerox.com.