Better, less expensive clean without megasonics
Engineers at NOVO Research, San Jose, CA, have developed a megasonic-free single-wafer ozone cleaning process — dubbed OzoneJet — that achieves high particle removal efficiency without damaging wafer patterns. This technology targets conventional ozonated-DI water cleans that are limited when ozone decays rapidly at high pH and elevated temperature. Further, this new process addresses the relatively high "chemical consumption" costs of 300mm single-wafer cleaning. This is the work of Yongbae "Joshua" Kim, Jungyup Kim, YongHo Lee, and HanSoo Cho.
Using many orifices in one or more radial nozzles, the OzoneJet delivers ozone gas directly to a wafer's surface in the presence of cleaning chemicals as the wafer rotates. Joshua Kim explains, "The pressures of individual columns of ozone gas from the orifices part the surface chemical layer at multiple points of contact, and make possible the direct reaction between the highly oxidative ozone species and the wafer surface. A given point on a wafer sees repeated exposures to chemical and fresh ozone." Conventional ozone-related processes using ozonated-DI water or diffusion of ozone through a layer are often limited because of ozone decay and lower ozone concentrations.
SEM micrograph reveals no pattern damage after a high- pressure jet process.
In evaluation tests, the NOVO engineers found that an HF OzoneJet plus ammonia cleaning chemistry enhanced particle removal efficiency by ~80% compared to cleans using just HF. "This is due to particles being removed and prevented from re-adhesion by the change in zeta potential by the ammonia," says Kim. Furthermore, addition of ozone to the ammonia increased particle removal efficiency to >95%.
Optimized to control pitting of bare silicon, the NOVO baseline includes consecutive applications of HF OzoneJet, DI water rinse, ammonia OzoneJet, DI water rinse, and Rotagoni drying; total process time is 105sec/wafer including drying.
Tests that included jet pressure two times normal for cleaning aluminum patterned wafers showed no pattern damage (see SEM). " The NOVO-jet process could be applied to FEOL, BEOL, and post-CMP cleaning," says Kim.
Kim explains, "Because the NOVO-Jet cleaning process does not use hydrogen peroxide or HCl, the amount of DI water and HF consumption is 2% of the traditional RCA clean. This is attractive for fabs adopting single-wafer processing, because typically these processes have required more costly higher chemical concentration and consumption to meet throughput requirements."
Technique improves range of new CMP tool
To counter the kinds of defects that will increasingly occur at 65nm when using spin rinse dryers — due to precipitates left in watermarks — a new CMP tool, Applied Materials' Reflexion LK, incorporates a Desica cleaner with an alternative drying methodology. This is opposed to the standard spin, rinse dry (SRD) technique, which is inefficient for low-k surfaces that tend to be hydrophobic.
"Using SRD on hydrophobic wafer surfaces, water runs off as a mass of random-sized beads, with the smaller ones drying up before reaching the wafer edge, leaving behind watermarks," says Konstantin Smekalin, product marketing manager for BEOL CMP-copper.
Cu/ULK CMP process window. Source: Applied Materials
To tackle the challenge of polishing mechanically weak low-k dielectric materials, the tool uses a down-force of 0.5psi; typical down-force pressures in CMP tools are ~2psi. "Once the threshold [at which damage to low-k materials may occur] was clearly established at 1psi, the conclusion was made that it was safe to operate at any pressure below 1psi," explains Smekalin (see figure). "Since 0.75–0.80psi did not induce any damage, none is expected at even lower pressures such as 0.5psi."
The operating principle of the LK tool is a rotational platform that the company says maximizes the available linear velocity, thereby boosting productivity. Using a radius of 9 in. and rotational speed of 350 rpm, the maximum linear velocity is calculated by Smekalin at 1650ft/min — a substantial difference from the maximum linear velocities calculated for other platform types (such as orbital: 350ft/min at 600rpm; and linear: 800ft/min).
Applied Materials is trying to woo users with upgrades that extend the capabilities of the tool to below 65nm without changing the platform.
"The tool can work for three generations now: 130nm, 90nm, and 65nm," explains Smekalin. "And with some technology upgrades, it can work below 65nm."
Wafers stack on copper Super-Vias
A set of multiwafer stacks — reportedly the first ever built with vertical through-silicon connections — has demonstrated the electrical connectivity needed for tightly integrated 3-D semiconductor chips. Engineers created these wafer stacks under the direction of Subhash Gupta, VP of process development at Tachyon Semiconductor Pte. Ltd., Singapore, using proprietary processes.
Tachyon's unique stacking process uses copper-to-copper thermal diffusion to bond standard silicon wafers without introducing adhesives or dielectrics. After the first two wafers are bonded, the top wafer is thinned and additional wafers are bonded and thinned in turn. The extreme thinning facilitates through-wafer electrical connections and heat dissipation, and ensures that future multilayer devices will fit into standard packaging.
Key to this integration is that before being bonded into a stack, each wafer is patterned with trademarked "Super-Vias" connectors embedded vertically in the silicon (see micrograph). Some of the Super-Vias are positioned to pierce only one wafer; others are designed to interconnect with Super-Vias on other wafers. Meticulous wafer alignment during the bonding process — with an Electron Vision aligner bonder — allows the Super-Vias to interconnect according to design, creating conductive paths that pierce two or more wafers.
As well as providing electrical connectivity, Super-Vias also address thermal buildup. Robert Patti, CTO at Tachyon, says, "Our copper Super-Vias act as efficient radiators, dissipating heat that would otherwise be trapped between the silicon layers. We have also minimized thermal buildup by 'ultra-thinning' each bonded wafer to only 13µm."
Each of Tachyon's latest wafer stacks contains three or four 200mm wafers. The Super-Vias are 4µm dia., embedded at densities as high as 14,000/mm2. Cross-section micrographs reveal that wafer alignment is precise to within 0.33µm, providing ample overlap for connectivity.
Tachyon engineers believe that future stacks can be built with smaller Super-Vias at higher densities.
"We are planning to build functional 3-D prototype chips before the end of the year," says Patti.
Technologies to improve 300mm substrate performance
New differentiating technologies are expected to boost substrate performance in the 300mm wafer generation — possibly bringing higher margins to silicon suppliers and certainly bringing them plenty of new demands for their R&D spending.
Wacker, Munich, Germany, says it will move its flatter, faster, two-sided grinding process into volume production before year's end. The company claims its process of grinding a free-floating wafer on both sides at once efficiently produces wafers with nanotopography that varies no more than 8.1nm in a 2¥2mm2 area, and no more than 18.5nm in a 10¥10mm2 area, better than the 2003 ITRS roadmap targets for the 70nm node.
The company worked with tool suppliers to make the flatter wafers, based on an idea for centerless grinding it got from the automotive industry's process for machining crankshafts. The tool floats the wafer on a cushion of water, while rotating it between two small grinding disks that move in opposite directions. The free-floating system prevents copying the surface waviness from the back of the wafer to the front when polishing. The new grinding method apparently does not remove the excess of material that previous free-floating methods did.
Wacker claims its implanted SOI wafers will match bonded processes on cost at 300mm. SOI is getting close enough to mainstream applications to attract the company's attention; it expects SOI to come into the mainstream at 65nm. Wacker is now sampling its SOI wafers, noting its high-energy implant of oxygen ions into the silicon can be done very accurately at the desired level, and claims it gets better layer uniformity than bonded alternatives.
The inside of Wacker's grinding tool.
Wacker's solution to the still problematic surface quality of all SOI wafers is very high temperature annealing, heating the wafer to 1300°C, while avoiding problems with wafer slippage at those high temperatures.
Wacker also counts on internal oxidation of silicon to precisely tune the layer thickness without CMP. It grows a top thermal oxide that eats into the lower layers to tune their thickness as desired, which also improves the micro-roughness on ultra-thin surfaces too delicate to stand up to CMP.
"Not enough volume of SOI is being shipped yet to tell much of anything about which approach will win out," says Gartner Dataquest principal analyst Dean Freeman of the two technologies. He notes IBM is using the implant process to put the insulating layer only in the parts of the wafer where desired.
Another variety of 300mm wafers will be strained silicon, a generation or two behind SOI, but likely to be in demand at 65nm too. "We expect it will hit the market with pretty good force at 65nm," says Freeman. "It may allow the industry to put off high-k gates until 45nm."