Among transistor manufacturers, perhaps the main measure of technical excellence is RDSON, the resistance of the transistor in its on state. This value needs to be as low as possible to improve current carrying capability, and to minimize power consumption. There are multiple ways of reducing RDSON: thick interconnect layers, smaller pitch — that also benefits die size and cost — and thinner wafers. All these techniques tend to be used to a greater or lesser extent.
The power semiconductor market is dominated by two sectors: power transistors and power management ICs (see "Power semiconductors at a glance"). From the viewpoint of the metal equipment provider, power transistors offer unique and testing challenges.
Power transistors fit into three categories: MOSFETs, IGBTs (insulated gate bipolar transistors) and bipolar transistors, differentiated on performance, functionality and power range. In power transistor design, the current passes through the actual wafer — the source is on the front and the drain is on the rear (Fig. 1).
Figure 1. Power transistor graphic.
Traditionally, discrete power manufacturers have used single level aluminum interconnects up to 8µm thick, usually deposited in last generation tooling. Figure 2 shows a representative SEM from such a scheme; minimal metal flow is apparent with poor step coverage. For this generation of device, delivering a smooth, near-planar metal surface is not necessary and the process method is simple, low temperature, and low cost.
Driven by key parameters such as RDSON, power transistor manufacturers are reducing pitch dimensions and as a consequence, the poor step coverage shown in Fig. 2 is becoming a potential liability. Thinning of metal inside the structure may limit current handling, and the deep narrow seams could become a wet chemical trap potentially compromising reliability.
Figure 2. Side and top view of traditional power interconnect, poor coverage, deep seams.
Flowing aluminium alloys to improve metal step coverage requires high temperature and the atomically clean interfaces delivered in a cluster tool. In addition, to prevent junction shorting through Al to Si interdiffusion, a strong diffusion barrier must be introduced between Al and the wafer; TiW, and increasingly, TiN, display excellent barrier properties. Through process and temperature control, seamless, near-planar thick metals can be deposited, displaying excellent step coverage (Fig. 3).
While providing many on-wafer benefits, introducing a flowed metal scheme into a power fab can be costly, reducing the already thin margins characteristic of power device manufacture. The main areas where costs can be added are flowed Al throughput and barrier strength.
A flowed Al process normally comprises two or three discrete steps, often reducing system capacity. Higher throughputs, however, can be achieved with >30wph possible for the images shown in Fig. 3.
Figure 3. Thick flowed Al over power structures using Trikon's Sigma fxP.
The main cause of reduced throughput stems from the steps normally taken to strengthen the diffusion barrier. As-deposited TiN is a columnar film and at temperature, Al can easily diffuse between TiN grains to react with the Si contact and short the device. The traditional way to circumvent this is to break vacuum after TiN deposition and with furnace or RTP treatments, "stuff" the barrier film with oxygen and block the fast diffusion paths. The technique is effective but dramatically cuts throughput; running the barrier layers and the subsequent Al step each at say, 30wph, gives a real throughput for the total stack of 15wph. Additionally, there is more wafer inventory and, when tool visits are increased, a greater potential for bottlenecks.
An in situ barrier strengthening process that allows the entire metal stack to be deposited in one system visit has been developed. The full sequence of degas, Ti/TiN, flowed metal is performed with one recipe without any recourse to vacuum break, delivering cost benefits through greater productivity and fewer wafers in progress. The technique works by treating the columnar barrier with low levels of oxygen inside the deposition chamber. After that, because Al does not flow well over surfaces exposed to O2, an additional thin layer of TiN is deposited to hide the treated layer from Al.
In contrast to what might be expected, the effect of the treatment on TiN resistivity is insignificant. Comparing the in situ process with a traditional vacuum break approach, Al flow characteristics are not affected and near-planar films are produced without any need for flow recipe change. Extensive barrier stress tests have been performed and the integrity of the new diffusion barrier remains intact for stress temperatures >500°C. An additional benefit of the new process is that the barrier is compressively stressed and serves to oppose the stress of the thick, tensile Al layer above. When compared to alternative techniques where a deliberately open structured, tensile TiN is deposited and then "stuffed" in an on-tool anneal chamber, wafer bow is reduced (Fig. 4).
Figure 4. Reduced wafer bow with in situ process (150mm wafer).
For a power manufacturer, reducing the wafer bow has two key benefits. First, a wider operating window at subsequent lithography steps has the potential to allow tighter patterning tolerances. Second, if these wafers are to be thinned, reduced frontside bow can be expected to increase wafer yield because low bow should reduce wafer breakage at backside deposition, or at dicing.
Backside solderable metals
Depositing a metal stack on the rear of the wafer forms the transistor drain contact. A three-layer stack of titanium for adhesion, nickel (or nickel vanadium) for solder/barrier, and silver passivation is typical, although other layers can be added depending on application, such as aluminium or gold.
Particularly for low voltage MOSFETs, one common method of reducing RDSON is to thin the substrate. Manufacturers using 150mm wafers are pushing wafer thicknesses below 100µm, with 65µm wafers in development. Those who have moved to 200mm wafers are developing wafer grinding techniques to deliver ~120µm thicknesses. These developments challenge metal system vendors, placing great importance on handling accuracy and reliability, and film stress control.
Film stress control and hardware development are two key aspects to excellence in backside solder metal deposition. Absolute minimum stress is not always the goal, often the ability to tune stack stress to oppose the bow of the incoming wafer is the objective. Handling modifications to enable gentle, reliable handling of fragile wafers can also be accomplished.
Film stress control techniques
The nickel vanadium solderable layer is the key to stress control. Naturally highly tensile as-deposited, NiV stress can be tuned over a wide range through a variety of input parameters:
- Process gas. Small additions of nitrogen into the processing environment will reduce NiV stress from +1GPa to +1MPa. The solderable properties of the layer are not significantly affected.
- Wafer temperature. Depositing NiV at low temperature has a major effect on film stress, giving the ability to move from GPa tensile into mid-MPa compressive. Although cold electro-static chucks have excellent cooling properties, some users view forced clamping of fragile substrates as a mechanical damage risk. An alternative is sub-zero chilled non-clamped platens, effectively chilling the wafers in the complete absence of any clamping force.
- RF bias. Applying wafer bias to the growing NiV film will move film stress from tensile into compressive.
In practice, stress control strategies use a combination of all or some of these factors to achieve the final objective: fully metallized ultra-thin wafers displaying minimum wafer bow.
Power device makers need to improve margins through product differentiation to drive key parametrics such as RDSON. As a consequence, the industry is seeing new technology requirements in terms of flowed interconnect schemes into finer structures over new barrier layers, combined with a rapid move to ultra-thin wafer handling.
The challenge for equipment makers is to deliver the required technology on common platforms in order to minimize operating costs, without compromising the high productivity goals set by the cost-sensitive power maker. New developments in interconnect processing over in situ strengthened barriers, plus stress controlled solderable layers on sub-100µm thin wafers make these goals achievable.
David Butler, Damian Lacey, Raj Jakkaraju, Trikon Technologies Ltd., Newport, UK
The authors would like to thank Clive Widdicks, Ian Moncrieff, and Steve Dennies of Trikon Technologies Ltd. for their contributions.
Contact David Butler, Technical Marketing Manager, Metal, at Trikon Technologies Ltd, Ringland Way, Newport, NP18 2TA, UK; ph 44/0-1633-414058; fax 44/0-1633-414180 ; email firstname.lastname@example.org.
Power semiconductors at a glance
The global power semiconductor market is estimated to be worth ~$12 billion with projected annual growth at ~15%. Power handling is a pervasive area of our industry with power management semiconductors present in various products such as PCs, cars, industrial control systems, and consumer devices. Recently, the power segment has performed better than other areas of the semiconductor industry for a number of reasons:
- IC trends. There is control of lower quiescent currents with tighter tolerances plus integration of multiple voltage output functions onto one chip.
- Battery charging and management. New battery chemistries affect charge control and protection. Plus, there is a need for better fuel gauging, and data collection on battery voltage/.current and temperature.
- Communications. Emergence of 2.5 and 3G handsets demand more power management content in the way of battery management and charging ICs.
- Automotive. A modern mid-size car might contain up to 50 ICs. The trend to greater electronic content will continue with the move to 42V power systems.