Dave Thomas, Yiping Song, Kevin Powell, Trikon Technologies Ltd., United Kingdom
The integration of low-k dielectric materials has proven to be a significant challenge for semiconductor manufacturers. Progress has been made, though, in etching materials. Results with a variety of low-k materials are presented, with indications that ITRS requirements can be met for at least several years.
Figure 1. Dielectric etch process for a) subtractive aluminum and b) via-first copper dual damascene. The barrier dielectric is removed following stripping of PR#2.
Surging demand for high-speed logic devices is driving the current change in metallization schemes (W/Al to Cu) designed to reduce line resistance. At the same time, or sometimes independently, the interline capacitance may be decreased by lowering the dielectric constant (k) of the insulator between the metal lines. Table 1 is taken from the 2000 ITRS Roadmap for logic devices and shows how the effective dielectric constant is predicted to change with the technology node. "Hybrid" schemes with mixed Al and Cu metallization are common. Here the overall risk of implementation is reduced by the introduction of Cu and/or a low-k dielectric at a limited number of device levels.
Choice of materials and deposition methods
Device manufacturers wishing to implement a new low-k film and Cu metallization simultaneously face a number of significant challenges. The situation is exacerbated by the variety of low-k material types and deposition methods available on the market. Carbon-doped silicon oxides (also known as SiCOH films) are an important class of low-k materials. Here, the reduction in k is achieved by simply doping a silicon oxide with methyl (-CH3) groups. The inclusion of the -CH3, bound to a Si atom, effectively terminates a proportion of the Si-O bonds. The result is an overall "loosening" of the lattice, a reduction in film density, and a corresponding reduction in the k value.
Table 2 summarizes some of the SiCOH films that are available on the market. Dielectric constants for these materials are typically 2.4-3.3.
Critical plasma etch processes
The plasma etching and resist/polymer strip steps are among the most critical for the successful integration of a low-k dielectric. Figure 1 shows typical dielectric etch schemes for both subtractive aluminum (Fig. 1a) and copper damascene (Fig. 1b) approaches.
To realize these types of device schemes during the etch process, it is necessary to:
- remove multilayers of dielectric;
- maintain a notch-free profile for optimum subsequent step coverage by the metal;
- achieve high selectivity to resists, which is especially important because: 1) resists get thinner and less resistant to the etch process as feature sizes decrease, and 2) 193nm exposed resists are significantly less resistant to plasma etching than those exposed at 248nm; and
- retain the k value during the etch and strip processes so that the ultimate device speed is not compromised.
When a damascene scheme is chosen, it also becomes very important:
- to achieve high selectivity to etch stop layers, especially since these are thinned to minimize the stack's effective k value;
- to minimize micro-trenching at the etch front; and
- to minimize aspect ratio-dependent etching.
Low-k dielectrics and etch chemistries
Various SiCOH films were identified in Table 2. The CVD and PECVD processes use (CH3)xSiHy (where x = 1-4 and y = 3-0) plus an oxidant such as O2, O3, N2O, or H2O2. Alternatively, the films may be spun-on from a liquid source. They can contain as much as 40 atomic percent C. Trikon's low-k Flowfill dielectric, for example, uses a CVD method and a (CH3)SiH3 + H2O2 chemistry to produce films with a tunable C content in the range 7-13% and a corresponding tunable k value in the range 2.4-3.4. SiCOH films are finding their way into gap fill applications employing subtractive aluminum and damascene applications in conjunction with copper metallization.
Figure 2. Etching of a) 0.3?m-dia. vias through Trikon's low-k Flowfill (k~2.9); b) 0.4?m-dia. vias through Honeywell's HOSP (k~2.5); c) 0.28?m-dia. vias through a Trikon dual damascene stack (k~2.8); and d) 0.29?m-dia. vias through a dual damascene stack containing the Applied Materials Black Diamond film (k~2.8) and BLOk (k~4.5-5.0) etch stop.
Table 3 shows the stoichiometry of Flowfill dielectrics with k values ranging from 4.2 down to 2.4. Concentration measurements were made by electron recoil detection analysis (ERDA) for Si, O, and C. Rutherford back-scattering (RBS) was used to measure H. Dielectric constants were determined via capacitance measurements on parallel plate electrical structures.
Low-k films require slight modifications to the chemistries that would normally be used for etching conventional SiO2. Generally, due to the high Si:O ratio, plasmas chosen are richer in fluorine atoms than those for conventional oxides. It is not unusual to use fairly simple gas mixtures such as CF4 (the principal source of F atoms) and CH2F2 (a polymerizing gas for improving selectivity and providing sidewall passivation). The choice of gas mixture depends on the precise application being considered.
Low-k via etching
Figure 2a shows 0.3µm-dia., ~4:1 aspect ratio vias etched through Trikon's low-k Flowfill material. The k value was ~2.9 in this case. The resist has been stripped from this wafer. Here there was a requirement to preserve resist during the "cap" etch so as to minimize the loss of critical dimension (CD) for the remaining stack, so the cap was etched in reactive ion etching (RIE) mode. The remaining layers were etched using helicon mode. (See "M0RI plasma etching" on p. 110 for more details on the etching equipment.) The result clearly shows that notch-free multilayer stacks can be etched by the simple selection of appropriate operating modes and chemistries. The etch rates of the oxide and low-k layers were ~3000Å/min and ~7000Å/min, respectively. Selectivity of these layers to the resist was in the range 3-4:1. We have found that Honeywell's HOSP etches in a very similar manner (Fig. 2b).
Figure 2c shows an example of a "via first" dual damascene scheme using ~0.28µm-dia., ~5:1 aspect ratio vias through a Trikon low-k damascene stack. Here the k value is ~2.8 for both the low-k material and the ~1000Å-thick etch stop layer. From the SEM picture in Fig. 2c, it can be seen that there is sufficient resist remaining after the etch is complete, and that no significant notching of the profile through the multilayer stack is evident. Here the low-k layers are etched at ~5000Å/min.
A very similar etch process can be used for the Applied Materials Black Diamond low-k film employing a proprietary etch stop material known as BLOk. Figure 2d shows a 0.29µm-dia., ~3.4:1 aspect ratio via through a multilayer of Black Diamond (k~2.8) and BLOk (k~4.5-5.0). The BLOk is ~500Å thick. In this case, the resist had a thinner starting thickness and was exposed at a wavelength of 193nm. Despite this, there is an appreciable amount of resist remaining after etching. For higher-aspect-ratio vias, however, this type of process may require the addition of a hard mask beneath the bottom antireflective coating (BARC) layer. Other work shows that the process can be extended to a 0.2µm feature size and ~4.9:1 aspect ratio.
Etch depth measurements show that aspect-ratio-dependent etching is negligible (~4%) for this process, between vias with diameters of 0.28µm and 0.2µm.
Table 4 illustrates the importance of multistep processing and multimode flexibility for dual damascene applications of this type.
Low-k trench etching
Following the via etch step of a via first, dual damascene application, trenches are etched down to the buried etch stop layer. Figures 3a and b show 0.3µm trenches etched through Novellus's CORAL. k values are typically 2.5-3.3 for this material. Here, helicon mode is used throughout to retain tight control over the CD during the etching of a thin BARC/low-temperature oxide stack (~80nm total thickness) and the subsequent low-k layer. The helicon mode also maintains a high etch rate (~8400Å/min in this case) for the low-k film. Figure 3a is a test structure down to the Si substrate. Figure 3b is a partial etch, showing the existence of a flat etch front.
Figure 3. a) 0.3?m trenches etched through CORAL low-k material (k typically 2.5-3.3), and b) a partial etch of the same structure, showing the flat etch front.
Figure 4a shows ~0.35µm trenches etched into the same dual damascene stack as in Fig. 2a. A partial etch of 0.18µm trenches through a Trikon damascene low-k material is shown in Fig. 4b. This partial etch demonstrates that it is possible to maintain a flat etch front.
We have previously described the application of a CARL dry develop technology to the fabrication of contact holes with feature sizes down to 25nm . Figure 5 shows that this technique can be readily applied to the etching of vias through low-k Flowfill with ~0.1µm diameter and ~7:1 aspect ratio. Here the k value was ~2.7 and the entire structure was etched in helicon mode. To our knowledge, these represent the smallest structures ever to be etched through a material with a dielectric constant of 2.7 using a commercially available plasma system. The ITRS Roadmap predicts that, for microprocessor devices, k values of 2.2-2.7 will be required for the 100-130nm technology nodes in 2004. It also postulates that, for DRAM devices, k values ranging from 2.5-3.0 will be needed at 100nm in 2005.
Figure 4. Etching through a Trikon damascene low-k material a) with 0.32µm trenches down to a low-k etch stop (both values ~2.8), and b) with a partial etch of 0.18µm trenches.
Magnetic zero resonant induction (M0RI) represents an enabling technology for these types of features that will need to be successfully fabricated during the next year or so. Clearly, this new result is not fully optimized, as there is a taper to the profile within the "base" layer.
Resist and polymer stripping
The low-k film must preserve its physical and chemical properties during the processing steps encountered during the fabrication of the device. If this cannot be achieved, then the perceived benefits of the low-k film, implemented by the designer, will never be realized. During via and trench etching of carbon-containing silicon oxide low-k films, the sidewall is passivated with a layer of fluorocarbon polymer, somewhat protecting the low-k film from the plasma during etching. Nonetheless, it is important that the plasma itself contains little or no oxygen because this could liberate carbon from the low-k film, changing its k value. Tests carried out on the properties of low-k Flowfill before and after etching show that there are no significant changes to the film.
Figure 5. 0.1µm-dia. contacts etched through low-k Flowfill (k~2.7) before resist strip.
Following the main low-k etching process, it is necessary to strip the resist and etch polymer residues from the wafer. Traditionally, plasma strip processes have used oxygen as the principal gas, removing the resist as volatile CO, CO2, and/or H2O, and the etch polymer as CO, CO2, COF2, etc. During the process, there is a significant danger that the oxygen could also strip out the carbon from the low-k film. Therefore, it is vital that the strip process be tested for its effect on the low-k film properties. Because of this, it is beneficial to make the strip chemistry as benign as possible to the carbon of the low-k film. Hence, strip processes containing no oxygen are being investigated by many etch vendors. Figure 6 shows Fourier transform infrared (FTIR) peak area ratios for low-k Flowfill films (k approximately 2.4) before and after stripping in oxygen-based and reducing (nonoxygen) chemistries. The peak area ratios are unchanged, indicating that, in this case, neither of the strip chemistries will compromise the bulk properties of the low-k Flowfill film. Similar data has been obtained when the low-k Flowfill is subjected to a wet strip using EKC 265.
Figure 6. FTIR peak area ratios for low-k Flowfill films (k~2.4) before and after stripping in oxygen-based and reducing plasmas.
Figure 7 shows the ~0.1µm-dia., 7:1 aspect ratio features from Fig. 5 after stripping using an oxygen plasma. There is no noticeable change in the shape of the holes through the low-k layer. Together, Figs. 6 and 7 show that it is possible to etch extremely fine structures through low-k dielectrics without adversely affecting either the k value of the film or the CDs of the features.
Figure 7. ~0.1µm-dia. contacts etched through low-k Flowfill (k~2.7) after resist strip in an O2 plasma.
Low-k dielectrics are currently finding their way into advanced integrated circuits in order to increase device speeds, but integration of the new materials creates a number of significant challenges. SiCOH films are an important class of low-k dielectrics. M0RI plasma etching is well suited to these materials because it offers multimode flexibility that can be fine-tuned to the etching of each material of the low-k stack. M0RI offers the ability to define vias (down to ~0.1µm) through some of the industry's leading low-k dielectrics designed for subtractive aluminum applications (Flowfill and HOSP) and vias/trenches (down to ~0.18µm) through a range of low-k materials designed for copper dual damascene (Trikon's damascene low-k, Black Diamond, and CORAL). Extendibility beyond the current requirements of the ITRS Roadmap has also been demonstrated.
The authors would like to thank LSI Logic's Santa Clara facility for their assistance in preparing this article and for providing some of the SEM pictures. We also acknowledge collaborative work on the 0.1µm features involving International Sematech, Infineon Technologies AG, and Clariant GmbH. Flowfill and M0RI are trademarks of Trikon Technologies. CORAL is a trademark of Novellus Systems. Black Diamond and BLOk are trademarks of Applied Materials. HOSP is a trademark of Honeywell.
- Y.P. Song et al., "Fabrication of Sub-0.1µm Contacts with 193nm CARL Photolithography by a Combination of ICP Dry Development and M0RI HDP Oxide Etch," Electrochemical Society Proceedings, Vol. 99-30, pp. 226-232, 2000.
Dave Thomas received his BSc in chemistry from Leeds University and his MSc in surface chemistry from the University of Bristol. He received his PhD in chemistry via a collaborative project with Trikon Technologies. Thomas has worked for Philips Components and Southampton University as a research associate, and for Nortel Networks as a principal research engineer. He joined Trikon in 1994 and is currently etch product marketing manager. Trikon Technologies Ltd., Ringland Way, Newport, Gwent NP18 2TA, UK; ph 44/1633 414027, fax 44/1633 414180, e-mail Dave.firstname.lastname@example.org.
Yiping Song received his BCc in physics in 1982 from Beijing Normal University, and his PhD in semiconductor physics in 1988 from the University of Ghent. He conducted research on thin film properties at Durham University and on plasma etch at the University of Bristol and the University of Glasgow before joining Electrotech Ltd. in 1995. He is now a principal engineer at Trikon Technologies, responsible for etch process development as well as customer support
Kevin Powell received a first class honors degree in physics from Bristol University in 1985. He has worked at Plessey Semiconductors, Qudos Limited, and National Semiconductor in Greenock, Scotland. He joined Trikon in 1993 and is currently the manager responsible for all aspects of etch processing, including process development and field process support.
Figure 1. Schematic of a Trikon M0RI plasma etch chamber.
M0RI plasma etching
Helicons are waves that propagate in radially confined magnetized plasmas for frequencies between the ion and electron cyclotron frequencies. They were first observed in gaseous plasmas in the 1960s and emerged as efficient plasma sources for microelectronics applications in the 1980s through the pioneering work of Chen and Boswell [1, 2]. It was Plasma Materials and Technologies, which became part of Trikon in 1997, that first reported results on the use of magnetic zero resonant induction (M0RI) plasmas for etching layers on Si wafers in 1992. Today, the M0RI plasma module is offered on Trikon's Omega 201 etch platform.
Figure 2. Trikon's Omega 201 M0RI etch tool.
Figure 1 is a schematic of the hardware used to create the helicon wave plasma. The helicon plasma is generated within a ceramic bell jar by an RF antenna at an excitation frequency of 13.56MHz and at powers in the range of 1000-2000W. An electromagnet is used to provide the magnetic field necessary to produce the helicon wave. This results in the propagation of plasma density downstream toward the wafer. A second electromagnet is used to control the plasma uniformity. The lower chamber of aluminum is surrounded by permanent magnets to minimize electron losses to the chamber walls.
The Si wafers are electrostatically clamped to a platen typically cooled in the range of -20°C to +20°C by recirculating dielectric fluid. This electrostatic chuck is also powered with RF at 13.56MHz and typically at powers in the range of 200-1000W.
The table summarizes the modes of operation of the M0RI plasma system (Fig. 2). The versatility shown is useful for etching low-k structures because it is possible to select the most appropriate operating mode for the particular type of wafer being considered. The plasma conditions of chemistry, power, pressure, etc., may also need to be adjusted. However, all of these can be programmed into the etch recipe at the user interface without the need to change any chamber components. By using the M0RI tool, there is no need for Si electrodes or additional Si surfaces to bias the process chemistry.
Omega is a trademark of Trikon Technologies Inc.
- R.W. Boswell, F.F. Chen, "Helicons the Early Years," IEEE Transactions on Plasma Science, Vol. 25(6), pp. 1229-1244, 1997.
- F.F. Chen, R.W. Boswell, "Helicons the Past Decade," IEEE Transactions on Plasma Science, Vol. 25(6), pp. 1245-1257, 1997.