Resistive quartz: A better process-fluid heating alternative
A new technology dubbed "resistive quartz" shows promise of providing advantages over conventional methods of heating fluids used in wafer processing without contaminating them. In addition, this technology is better able to handle changing process flow demands reliably.
The technology is a GE 214 semiconductor-grade quartz tube with a ridged interior wall and an intimately compliant, thin, resistive film on the exterior. The effect is a piece of quartz tubing that heats up as if it were a heating element. As fluid passes through the tube, there is a minimal amount of thermal resistance between the heat source and the fluid. The low thermal resistance allows the element to operate under 300°C. Resistive quartz is a proprietary product made by Trebor International, West Jordan, UT, with multiple patents issued and others pending.
A comparison of the response of heaters using resistive quartz and IR, the latter from published data, for 7.5 liters/min flow at 85°C.
Conventionally, wafer processing has used PTFE Teflon-coated immersion or IR lamp heaters. With immersion style, the element is immersed in a process fluid, and runs a risk of breaching the tube if the element fails due to extreme temperatures. To minimize this risk, these units are typically run at a low watt density that results in a large, sluggish thermal mass that can trap particles.
IR heaters are sluggish due to a large thermal resistance between the heat source and the fluid, often causing the element to operate over 1000°C. Also, IR quartz vessels are often complex, expensive, and fragile designs. The sluggishness of these conventional technologies often requires control via complex algorithms to maximize performance (i.e., an attempt to compete against the laws of physics).
The most impressive application advantages of the resistive quartz technology comes from its cleanliness, heating characteristics, and robustness. For example, resistive quartz will not contaminate in the event of a heating element failure. The coefficient of thermal expansion for quartz is 1/200th that of PTFE, so as a heater made with resistive quartz cycles, it will not move and generate particles.
Compared to immersion and IR style elements, resistive quartz responds rapidly to process changes because of low thermal resistance and low thermal mass combined with high power densities (see figure). The simple quartz construction eliminates mechanical stress concentrations to provide a rugged heating package, virtually free of broken quartz.
A move to single-wafer cleaning: Timing is the biggest challenge
One of the biggest trends in wafer cleaning is single-wafer wet cleans at the critical pre-gate level. Strictly speaking, PVA brushes (scrubbers) used in post-CMP cleans can be considered a single-wafer cleaning process, and some fabs use single-wafer etching for backside thinning and layer removal. But for critical cleans, single-wafer cleaning is new.
At 180nm and smaller, traditional cleaning technologies can damage device structures, forcing a reduction in applied energy and/or time. Thus, smaller particles require higher energies to free them from the wafer surface. One solution is the application of megasonic technology.
Verteq's Goldfinger Mach2 provides both single-wafer megasonic cleaning and surface tension gradient drying in the same module.
There are a number of theories as to how megasonics works, but it is clear that, if done right, good results are produced. Mark Beck, CEO of ProSys, Campbell, CA, says megasonics is a different way of boiling water.
Instead of heat, megasonics changes localized pressure in the fluid a million times a second, creating a void (cavitation). During cycling, gases are pushed in and out of the void until it collapses, releasing the energy required to free small surface particles. Higher frequencies increase cavitation, with 1MHz producing bubbles one micron in diameter.
Therefore, higher frequencies should be more effective for cleaning devices with higher aspect ratios but not necessarily. A 1.5 and 2MHz frequency will produce smaller bubbles, but their potential energy and corresponding ability to remove a particle will also decrease, noted Beck.
Timing is the biggest challenge in single-wafer cleaning. It is clear that batch cleaning times of 20-50 min using standard RCA cleaning must be reduced to 1-2 min, according to Paul Mertens, leader of the ultraclean processing group at IMEC in Belgium. In this short time, cleaning, rinsing, and drying have to be completed. One approach reduces the number of chemistries, and thus steps, to one or two. IMEC has demonstrated success with a two-step process using ozonated water with HF treatment. More recently it has shown success with mixtures containing ammonium hydroxide and peroxide with chelating agents for single chemistries.
To reduce drying times, spin dry comes to mind as the fastest, simplest approach. However, it has been insufficient for critical levels, leaving residue on the wafer and watermarks on exposed silicon surfaces. Most critical are surfaces containing hydrophobic regions such as bare silicon or some of the low-k layers. IMEC has concentrated efforts on Lineagoni (linear motion) and Rotagoni (rotational motion) drying technologies. Each applies the Marangoni effect, a surface tension gradient effect that creates a force on parts of the liquid, resulting in effective local scale liquid removal, while minimizing evaporation, noted Mertens. The results from tests on 200mm wafers have been impressive: a 30-40x improvement over batch drying times, from 7-10 min to 10-20 sec.
Current dry cleaning methods often used for surface preparation are not effective in removing particles and metal contaminants. With the introduction of porous low-k materials or air gaps, this may change since liquids can alter material characteristics of porous films, says Mertens. At this point, single-wafer wet cleaning is taking off with the introduction of Verteq's Goldfinger Mach2 (see figure on p. 20), a cleaning system that provides both single-wafer megasonic cleaning and surface tension gradient drying in the same module. Other single-wafer clean systems are due out in the next few months.
Bell Labs touts first molecular-scale FET
Scientists from Lucent Technologies' Bell Labs have made the first molecular-scale transistors with channel lengths 100x smaller than nanotubes and 10x smaller than state-of-the-art silicon transistors. The potential of these devices is the continuation of Moore's Law beyond the physical limitations of silicon and current chip technology.
Thus far, molecular devices have been two-terminal structures such as rectifiers and switches, although the possibility of three-terminal devices has been reported. Bell Labs researchers, led by Jan Hendrik Schon, have developed a molecular-scale, vertical field effect transistor (FET), demonstrating "gain" for electronic transport perpendicular to a single molecular layer, ~10 to 20Å, by using a third gate electrode.
An illustration of the molecular-scale transistor, roughly a million times smaller than a grain of sand.
The FET is built on a highly doped silicon substrate, and sandwiched between two gold electrodes; a monolayer of thiol, an organic compound, provides the medium for amplification. Square notches are patterned on the substrate using conventional lithography and anisotropic etching, and SiO2 is used as the gate insulator. At the bottom of the notch, gold is thermally evaporated, forming the gate electrode, and is dipped into a solution of thiol, conjugated molecules consisting of carbon, hydrogen, and sulfur. During evaporation, the molecules self-assemble vertically, the thickness of which determines the channel length. A vertical trench in a cooled substrate serves as a shadow mask for the drain electrode, forming a contact region ~0.8 x 0.1µm2.
In this research, six forms of thiol were used to make self-assembled monolayer FETs or SAMFETs. Since conduction takes place within 50Å from the semiconductor-insulator interface, only several thousand molecules could be probed. The results from all six compounds exhibited similar performance and current-voltage characteristics, stated Schon.
In particular, the drain current could be modulated by approximately five orders of magnitude with applied gate bias. The SAMFETs are normally off p-channel transistors, so a negative gate voltage increases the conductance of the channel.
Typical threshold voltages were approximately -0.2V. No degradation was observed with modulation frequencies up to 105cycles/ sec and no resonant tunneling features or charging effects were observed in room-temperature characteristics. Subsequently, the researchers combined two SAMFETs to make an inverter, a building block of more complex logic circuits. A gain of six was obtained.
While development is still under way, the goal is to have a viable technology in the 2012 timeframe when the physical limits of current IC technology run out.
A new plasma-enhanced atomic layer deposition (PEALD) tool from Genitech Inc., Daejon, Korea, promises more flexible chemistries and faster processing for ultrathin, conformal films. The tool was described by Wonyong Koh at a Gate Stack Engineering conference at Semi Southwest in Austin, TX. The tool uses a folded lateral reactor design to suppress turbulence for a rapid gas supply, and offers a small footprint, according to Koh. He reported using the tool for Al2O3 and Ta2O5 films, and said that some Japanese DRAM manufacturers were already using tantalum pentoxide for DRAMs although this was not yet being done in Korea. This design eliminates the purge pulse steps required in ALCVD systems, and thus speeds throughput, and plasma produces very high quality films with excellent step coverage and uniformity. It may be applicable to high-k thin gate dielectrics, offering a much wider range of chemical sources than are usable in CVD equipment, according to Koh. Ta2O5 films by PEALD showed much smaller leakage current than films made by conventional MOCVD and ALD, Koh reported. The dielectric constants, calculated from the capacitance values, are in the range of 17 to 21, Koh said. Howard Huff of International Sematech, the session chairman, asked about wafer damage from the plasma, and Koh said that it had not proven to be a problem for DRAM devices.
Modelers at Sandia National Laboratories are helping micromachine designers choose the device they want fully fabricated through new nano-modeling programs. The need for previewing is important because microdesigns for telecommunications, inkjet printing, and medical and auto safety devices to name just a few are fighting for dominance in new, still unestablished fields, the research lab said. For this reason, researchers Vic Yarberry and Craig Jorgensen at Sandia have crafted 2D and 3D modeling programs to work with MEMS developers. The 3D program allows designers to twirl their virtual microdevices like airplane parts, the researchers explained, the still-imaginary part viewed from any perspective. Unworkable portions of the design can be changed or eliminated before not after fabrication work is paid for at the foundry. The simulation process takes time, anywhere from seconds to hours, but it's still a lot faster than waiting months to see what modifications should have been made.