Michael A. Corbett, John C. Davis, Kline & Co. Inc., Little Falls, New Jersey
The combined forces of recession and technological upheaval have created confusion in the semiconductor industry this year, but the dust is settling over the issue of low-k dielectrics at the 130nm design node. The two early winners are CVD organosilicons and spin-on organics. The prime commercial products in these categories are Applied Materials' Black Diamond process from Dow Corning, which consumes organosilane-type precursors from companies such as ATMI, Dow Corning, and Schumacher, and Dow's SiLK, respectively. The list of fabs that have announced for one or the other, or a few alternatives, is already long (see table) and getting longer.
Attention is now turning to the 100nm design node. Dow Corning, Honeywell, and Shipley have stated that this node which could start pre-production evaluation and materials selection next year for logic and by 2003 for memory  is now their primary market focus for spin-on precursors. Some degree of "extendibility" will be required at this node: Dense dielectrics that are going into use at the 130nm node may need some porosity to achieve the k values required for 100nm, which are targeted at 2.2 for logic and 3.0 for memory. This will certainly test the limits of current CVD technology, but will probably not knock it out altogether, as many companies, including ATMI, Dow Corning, and Schumacher have developed novel precursors allowing ASM, Applied Materials, Novellus, and Trikon to experiment with dielectric films having k values approaching 2.2.
By the 70nm design node, however, the competition may be decided in favor of spin-on solutions, because the porosity requirements for achieving a low-enough dielectric value may be too demanding. This decision could occur as soon as 2004. CVD should still have a place at this node for SiC hard mask and stop layers, which exhibit slightly better k values than silicon nitride. Further complicating this situation, however, several companies, including Honeywell, have announced development programs targeted at low-k spin-on cap layers.
The market today
While the industry downturn has certainly clipped overall semiconductor production, the consumption of low-k dielectric precursors is up this year; total volume, however, is still quite small. Sales of low-k precursor chemicals are expected to reach $29 million in 2001. This compares with $23 million in 2000, and <$5 million in 1999. Overall low-k product sales increased by about 25%, even in a down year for the industry.
Figure 1. Via-first integration schemes.
About one-quarter of this is for chemical sales of such leading-edge precursors as SiLK and Z3MS. Half of it is for spin-on dielectrics, such as Dow Corning's FOx, which may have applications unrelated to time-delay (RC) improvements. Another quarter is for CVD materials, mostly SiF4 to make fluorinated silicate glass (FSG), a faux low-k material that has seen wide application at the 180nm node, but so far, has only one taker (Intel) at 130nm. Recent research conducted by Kline & Co. indicates that there may well be more fabricators adopting FSG at the 130nm node in 2002. These companies are not yet satisfied that the integration issues associated with leading-edge low-k materials have been completely resolved, and they may delay implementation of true low-k materials until 2003. The bottom line is that only about $6 million has been spent on the new alternatives this year.
Figure 2. Interconnect deposition counts and chip production, 2000-2005.
The applications for low-k are mainly in semiconductors that incorporate copper interconnects. The main exceptions to this are the LSI application, which integrates a CVD organosilicon low-k material with aluminum interconnects, and many of the 180nm node and higher applications that typically integrate FSG with aluminum. It is ironic that low-k dielectrics have become so intertwined with copper integration. When low-k dielectrics were first investigated in the mid-1990s, most people thought that time-delay problems would best be solved by sticking with aluminum lines and tungsten vias while incorporating low-k dielectrics.
Figure 3. Growth rates of low-k and all interconnect dielectrics, 2001-2005.
The alternative, replacing aluminum with copper and sticking with conventional dielectrics, was perceived as too difficult. IBM changed that thinking in 1997, when it produced a logic chip that took the copper-first route at the 180nm design node. As soon as the 130nm node arrived, copper alone was not enough, and low-k dielectrics were needed as well. What IBM did, in effect, was to reverse the order of implementing these technologies. It decided, and nearly the whole industry agreed, that integrating copper is easier than integrating low-k dielectrics, so it is preferable to implement copper first.
Since copper is used in both the via and line levels, dual damascene construction is typically employed. The integration preference for low-k dielectrics is for via-first schemes, as shown in Fig. 1, which shows three via-first methods. Scheme 1 would be expected with conventional dielectrics, as well as with such processes as Black Diamond and Novellus's Coral. It also includes CVD-based nitride stop layers. So long as the dielectric is present, the main problem with this is the difficulty in stripping all of the resist out of the deep via, which in some cases can cause resist poisoning. Two ways out of both these problems are demonstrated in Schemes 2 and 3. Scheme 2, suggested by a group spearheaded by International Sematech and JSR Corp. , eliminates this problem with a dual hard mask at the top, which prohibits the resist from getting into the via. In this process, the hard masks are etched, one by one, to the widths of the via and trench, respectively, and then the dielectric layers below are etched. These schemes also substitute SiC, a CVD material, for silicon nitride stop layers, and use JSR's spin-on methyl silsesquioxane material. A similar approach, used by IBM in its first integration with Dow's all-organic SiLK (also a spin-on), is shown in Scheme 3. It depends on a timed etch, rather than a stop layer, to form the trench.
Consider that Scheme 1 is an all-CVD process, Scheme 3 is all-spin-on, but Scheme 2 is a mix of CVD and spin-on, requiring more costly movement back and forth between tools. Efforts to replace the via stop layer with spin-on materials, mentioned previously, could significantly lower cost-of-ownership (COO) for the spin-on option.
The market tomorrow
One way to estimate the future market for dielectrics is to look ahead to wafer-pass depositions of dielectric, and to include in this analysis ITRS Roadmap goals for k values. Such an exercise will show that overall depositions will rise as a result of increases in interconnect layer counts, tempered by the ups and downs of overall industry growth. The types of low-k dielectrics that are put into commercial use will vary according to their k value, integration schemes, and COO issues. FSG may be king right now, but it will drop out of the picture below the 130nm level. With a targeted k value of 2.2 for the 100nm node, current commercial versions of CVD organosilicons, as well as dense spin-on dielectrics, are not expected to get past this node in their current form. Development efforts are well underway from both camps to incorporate some sort of porosity at 100nm and below.
Figure 4. Low-k depositions by type of precursor, 2000-2008.
Low-k dielectrics of all types account for a mere 2% of all interconnect dielectrics today, but by 2005 they should account for at least 10%. This small percentage helps explain why this market has been unaffected by this year's big market swing. Semiconductor output has declined more than 20% this year , and interconnect depositions have similarly fallen, yet low-k depositions have risen approximately 15% (Fig. 2). Interconnect deposition counts should spring back smartly in 2002, but low-k will really take off, thanks to a combination of an industry upturn and rapid ramp-up.
The rapid growth in low-k dielectric depositions will be driven by an average annual growth rate exceeding 75% from 2001 until 2005 (Fig. 3). By that time, the market for low-k precursors will be approximately $300 million.
CVD versus spin-on
These methods are tied for now, but which process will win in the long run? This is one of the most debated questions in the semiconductor industry today. Both sides have a big stake in the outcome: Tool suppliers are looking at billions of dollars in new CVD deposition equipment and chemical suppliers are looking to recoup development costs ranging in the $50 million neighborhood.
According to research conducted by Kline & Co., the answer is "spin-on," at least as long as CVD proponents don't surprise the world with a breakthrough technology. To demonstrate this prediction, we must stretch the forecast all the way to 2008 a daring task given the fast rate of change in this industry (Fig. 4).
As seen in Fig. 4, there should be two breakpoints in the market in 2004 and 2007. The year 2004 represents the end of the initial ramp-up and a maturity of sorts in the industry. At this point, the world should be able to declare low-k a mainstream process, as it will account for 10% or more of all interconnect dielectrics. The issue of CVD versus spin-on will still not be settled, however. That will occur around 2007-2008, the same time that another burst of growth will occur as the industry goes full tilt with 70nm-node wafers. The main beneficiaries of this growth will be spin-on organics and organosilicons, as well as spin-on inorganics in the form of porous oxide, which will be making their first important appearance in the market. The others may lose share and fail to gain acceptance in the most advanced programs.
- ITRS Roadmap, preliminary revisions to 1999 ed., 2000.
- K. Mosig et al., IITC 2001.
- McClean Report, IC Insights, July 2001.
Michael Corbett is a director and John Davis is manager of research for electronic chemicals and materials at Kline & Co., an international consulting firm assisting clients with growth-based and performance-enhancing initiatives in the specialty chemicals, performance materials, and advanced process technologies industries. Steve Holland also contributed to this article. Kline & Co. Inc., 150 Clove Rd., Little Falls, NJ 07424; ph 973/435-3457, e-mail firstname.lastname@example.org. For more information on the source of this article, Kline & Co.'s reports The Global Outlook for Dielectric Materials in Semiconductors and Dielectric Materials in Semiconductors to the Sub-0.10-Micron Design Rule, contact Michael Corbett at the address above.