In semiconductor fabrication, a polymeric stress buffer layer between the IC final passivation layer and plastic molding compound interface is often required to protect the delicate layers of oxide and circuitry on the silicon surface from the stresses induced by the molding compound during operation of the chip. The stress buffer or overcoat is applied and patterned as the last step in traditional wafer fabrication. The coating also affords protection to the wafer during subsequent backgrinding and dicing assembly processes, which can be rigorous - and expensive if wafer damage occurs.
Polyimide coatings have become the material of choice for most stress buffer applications. Polyimides are high in molecular weight and have a fully aromatic polymer structure. These coatings can be applied at the wafer level in the form of a polyimide precursor, using standard coater tracks in a variety of different film thicknesses. Thermal curing converts the precursor into an intractable polyimide (PI) film. The associated cured film properties have been well documented and are well suited for most semiconductor applications. Polyimides are thermally stable to temperatures approaching 500°C, have elongation values of 50% or greater, and are highly resistant to most wet and dry processing chemicals used in production fabs. Cured film properties are frequently optimized for a given application by changing or modifying the polyimide backbone.
Fully aromatic polyimides are not inherently photosensitive. These polymers can be made photodefinable (PD) through the attachment of a methacrylate-based photo-polymerizable moiety onto the polyimide backbone using an ester or ionic linkage. Like traditional photoresists, photodefinable polyimides can be readily patterned on i or g-line semiconductor exposure tools. The improved resolution associated with photodefinable polyimides, in contrast to wet-etch polyimides, also permits the overcoat to function as a resist. Patterned polyimide overcoat layers can be readily used as a dry etch mask for patterning underlying silicon nitride passivation, creating a "single mask" stress buffer/passivation etch process for integration into high-volume semiconductor production.
Tight control difficult
In 1995, the LSI Logic fab in Colorado Springs implemented a wet-etch, "single mask" polyimide process on all products. Non-photo definable, self-priming DuPont PI-2573 polyimide was patterned in conjunction with a positive photoresist and a standard TMAH developer. The 2µm polyimide overcoat layer functioned as both a dry etch mask for patterning the underlying oxynitride passivation, and as a scratch protection and stress buffer layer. Due to the precise pattern definition requirements of single mask processing, the wet-etch polyimide process had a narrow process window and had to be tightly controlled. As a result, critical dimension control was difficult in day-to-day production in the fab. Some other key issues were:
- Process latitude - extensive rework rates of up to 30% were not uncommon.
- Cured film thickness was limited by resolution requirements to <3µm.
- Molding compound adhesion was not optimal, resulting in reliability concerns.
- The polyimide had a short room-temperature shelf life.
LSI began to explore other options for patterning the passivation layer to ease the resolution constraints of the existing polyimide wet-etch process. An additional positive resist process to pattern the oxynitride prior to polyimide application was considered. However, a two-mask passivation/overcoat process would significantly increase the total number of production and inspection steps required, and lengthen process cycle time.
A new aqueous-processing, negative-tone, photodefinable polyimide (introduced by HD MicroSystems, a joint venture between DuPont and Hitachi Chemical), offered superior resolution compared to wet-etch polyimide processing. In addition, the photosensitizers utilized in the new formulation were optimized for i-line lithography tools such as the 8-in. i-line steppers used at the LSI Logic fab.
The polyimide backbone was different from that of PI-2573, and was optimized for improved adhesion to nitride layers and the plastic molding compound for improved reliability. Most important, the new product (PI-2771) could be developed with standard TMAH-based developers that were in use on the positive resist developer tracks in the fab.
Processing steps reduced
The PD polyimide technology could potentially enable LSI to retain its single mask passivation/stress buffer process, use existing capital equipment, and increase throughput. Eliminating the need for photoresist (PR) coat and strip meant that the total number of polyimide processing steps could be reduced by one-third compared with the previous polyimide wet-etch/PR process. The superior resolution and adhesion characteristics of the new material would also permit the application of a thicker stress buffer layer. This increased film thickness, combined with improved adhesion, was expected to have good device reliability.
The potential drawbacks of the new technology were an increase in raw material costs compared to non-photosensitive polyimide, and the cost of converting the necessary photomasks from positive tone to negative. It was decided, however, that the potential increase in throughput and reduced rework associated with the new polyimide technology could outweigh these disadvantages.
Process integration results
Integration of the new polyimide process was relatively straightforward, and the final in-fab process was finalized within a few days. Some key variables fine-tuned from the existing process were soft bake time and temperature, exposure energy, post-exposure bake, and develop time/technique (which evolved into a two-puddle process). Cured film thickness in creased from 2 to 4.5µm after final cure. Bond pads and scribe lines were clearly defined (see figure).
Bond pads, comparing PI-2573 & PI-2771 resolution.
The new process was able to repeatedly pattern 10µm lines and spaces and 13µm via holes in 4µm cured polyimide films using a 0.26N TMAH-based aqueous developer. Patterning was insensitive to underlying wafer topography, with im proved resolution and excellent resistance to nitride etch processing gases. It was quickly determined during trial testing in the fab that the new polyimide could be readily integrated into the desired single mask passivation/stress buffer process scheme.
An improvement in process latitude and room temperature stability was also observed in the early test stages of process integration. The new product demonstrated five-month RT stability. No discernible difference was observed in pattern quality in 0-50 hr hold-time experiments between coat expose and develop, nor were there any discernible effects on end-of-line transistor or process parameters.
Rework rates for the original wet-etch overcoat process sometimes approached >1000 wafers/month. The inherent simplicity and wider process window associated with the new process reduced rework to less than an average of 150 wafers/month.
Final probe yields were also unaffected. LSI realized an 18% reduction in the cost of ownership in this process module, based on cost/wafer for each area of expenditure in the process flow, which included throughput, rework rate, cost of materials, and inspection time.
The new single mask polyimide process was tested and qualified for reliability on three different generations of part numbers using three different packaging technologies: BGA, PLCC, and PQFP. Splits were done comparing PI-2771, PI-2573, and no polyimide overcoat. Test methodology included the following: Sonoscan for delamination, electrical tests for shorts and opens after conditioning, and decap of conditioned parts for bus or corner anomalies. Key findings were zero fails for preconditioning, temperature cycle, high-temperature operating, pressure cooker, and storage life environmental stress tests. A 44% improvement was also realized in substrate-to-package delamination fails at 500 cycles vs. a no-polyimide passivation process.
Devices packaged with the thicker, photodefinable polyimide stress buffer also readily passed JEDEC Level 3 reliability testing. LSI certifies all new part numbers produced at the Colorado Springs fab to this standard.
Polyimide stress buffer layers are a proven materials technology for improved device reliability. Through the introduction of an aqueous-processable, photodefinable polyimide, LSI Logic was able to use a more robust and simpler process flow at a reduced cost. The new material is now used on most CMOS ASIC integrated circuits produced on the 8-in. line at the Colorado Springs fab. These devices are applied in a variety of end uses, including cell phones, laptop computers, workstations, disk drives, and cable set-top boxes.
Stephen Hall received his BS in electrical engineering at Colorado State U. In 1996, he joined Symbios Logic as a photolithography process engineer. This fab was later acquired by LSI Logic, 1635 Aeroplaza Drive, Colorado Springs, CO 80916; fax 719/573-3904.
Craig Schuckert received his BS in chemistry in 1973 and his MA in communication in 1977, both at Colorado State U. He joined DuPont in 1978 and is product manager for HD Microsystems, a joint venture between DuPont Co. and Hitachi Chemical Co.
Stephen Hall, LSI Logic, Colorado Springs, Colorado
Craig C. Schuckert, HD MicroSystems, Wilmington, Delaware