Expanded CV test system

Expanded CV test systems

The System 80 Series of CV measurement instruments has been expanded to include I-V testing, analysis software, and integration with hot chucks and probers. These systems can provide simultaneous quasistatic and high-frequency C-V testing, improving measurement accuracy when characterizing interface trap densities and doping profiles in semiconductor wafers. The systems can perform similar tests on thin-film transistors used in AMLCD panels, and are particularly suited to very thin oxide testing and characterization. Model 82-WIN includes all instrumentation, cables, and software necessary for the user to construct a complete simultaneous C-V system. It operates in a Windows environment with Metrics-ICS software, and its capabilities include: oxide thickness and gate area; series resistance; flatband C and V; threshold voltage; effective oxide charge density; metal-semiconductor work function; average doping, using true Cmin; band bending; and bulk potential. Keithley Instruments Inc., Cleveland, OH; ph 440/248-0400, fax 440/248-6168, e-mail product_info@keithley.com, www.

Font Sizes:

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.


VIDEOS

Electroiq 2 EIQ2

NEW PRODUCTS

Multitest announces ecoAmp for high-power applications

May 8, 2013 Multitest announces that its ecoAmp high power Kelvin contactor successfully passed a challenging evaluation for an automotive ...

EV Group rolls out EVG120 processing system

May 7, 2013 EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, t...

Quartz Imaging introduces automated measurement for semiconductor images

April 30, 2013

It can be very time-consuming for engineers to measure the various features of an X-SEM image of a semiconductor device.

Axcelis launches Purion XE high energy implanter

April 30, 2013 Axcelis Technologies, Inc. today announced the introduction of the Purion XE next generation single wafer high energy implanter...

TECHNOLOGY PAPERS

Rapid Defect Indentification with Layout-Aware Diagnosis

Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are...

Flip Chip Devices get Flat and Happy

Thin is definitely in, but what our modern flip chip devices really want is to be flat and happy! As flip chip die have become increasingly thinner in recent...

WEBCASTS

Surface Cleaning and Preparation

This introduction requires the development of new critical and selective cleans tackling galvanic corrosion, pattern collapse both in FEOL and BEOL...

450mm Status Report

Hear from the G450C General Manager, Paul Farrar Jr., on the current status of activities, key milestones and schedules, and imec’s senior business...

Join The ConFab discussion

Tue Feb 26 11:27:00 CST 2013

Questions and answers on FD-SOI

Fri Jan 04 14:56:00 CST 2013

Present your ideas at The ConFab in 2013

Mon Nov 26 09:04:00 CST 2012

The ConFab 2013 countdown begins

Thu Aug 09 16:18:00 CDT 2012

The ConFab: Big data is here

Sun Jun 03 19:19:00 CDT 2012

SUBSCRIBE

LATEST ISSUE

05/01/2013
Volume 56, Issue 3

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS