Significant role seen for selective epi and Si3N4 CMP
Selective epitaxial silicon-germanium deposition and Si3N4 CMP could be significant processes for 4-Gbit DRAM technology. These processes were used at NEC`s ULSI Device Development Lab in Kanagawa, Japan, to fabricate a contact pad structure characterized by large 70-nm (0.07-?m) alignment tolerances for both DRAM word line and isolation regions. The final structure is a 135-nm2 folded-bit-line memory cell in one of NEC`s 4-Gbit DRAM designs, using a 120-nm design rule (see figure).
An NEC 4-Gbit DRAM memory cell process sequence: 1) word lines with SiO2 cap and side wall, 2) anisotropic epitaxial silicon pads on n-active regions, and 3) Si3N4 interlayer dielectric film after CMP. (Source: IEDM 1997)
As of early 1998, this is the smallest DRAM cell ever reported, well within the predicted 200-nm2 DRAM memory cell size needed for 4-Gbit DRAMs, as indicated by forecasts of DRAM scaling. Further, the alignment tolerances achieved are 50-100% better than with previous processing methods for similar device structures. Alignment tolerance, especially between contact holes and word lines, is directly related to product yield.
Similar processes are troubled by incomplete self-alignment - where word lines are aligned but isolation is not - and by fusing of adjacent epitaxial silicon pads over isolation regions, caused by lateral selective epitaxial growth.
After shallow trench isolation and formation of the word lines, the silicon pads grow anisotropically during an NEC-proprietary selective-silicon epitaxial process. These pads contain 5% germanium and 9?1019 phosphorus atoms/cm3 doping. The process grows the pads as high as 350 nm. The next steps deposit a 200-nm thick Si3N4 interlayer dielectric film and planarizes this layer with CMP until the silicon pads are exposed. Subsequent SiO2 deposition, oxide CMP, e-beam lithography, and RIE with high SiO2 to Si3N4 selectivity form the necessary contact holes. Even if some misalignment in any direction occurs during contact hole lithography through the SiO2 interlayer dielectric, contact hole etching stops at the surface of the Si3N4 layer and silicon pads.
The NEC team who developed this process believes it will prove to be one of the most useful process technologies for 4-Gbit DRAM designs. - P.B.